当一级地址转换被禁用时，数据访问被分配为Device-nGnRnE内存类型，而指令访问根据SCTLR_ELx的I位决定其属性。I位为0时，访问为non-cacheable和outer shareable；I位为1时，访问为cacheable，具有特定的缓存策略。关闭MMU后，不正确对齐的指令访问可能导致CPU故障。
开启/关闭mmu后访问的情况
D5.2.9 The effects of disabling a stage of address translation
All other accesses
For all other accesses, when stage 1 address translation is disabled, the assigned attributes depend
on whether the access is a data access or an instruction access, as follows:
-
Data access
The stage 1 translation assigns the Device-nGnRnE memory type.(没有关闭MMU之前，内存访问是normal类型，关闭mmu后，内存访问变成了设备类型的)
-
Instruction access
The stage 1 translation assigns the Normal memory attribute, with the cacheability and
shareability attributes determined by the value of the SCTLR_ELx.I bit for the
translation regime, as follows:
When the value of I is 0
The stage 1 translation assigns the Non-cacheable and Outer Shareable
attributes.
When the value of I is 1
The stage 1 translation assigns the Cacheable, Inner Write-Through
Read-
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