armv8中开启或关闭mmu对内存和指令的影响

开启/关闭mmu后访问的情况

D5.2.9 The effects of disabling a stage of address translation

All other accesses

For all other accesses, when stage 1 address translation is disabled, the assigned attributes depend

on whether the access is a data access or an instruction access, as follows:

• Data access

The stage 1 translation assigns the Device-nGnRnE memory type.(没有关闭MMU之前，内存访问是normal类型，关闭mmu后，内存访问变成了设备类型的)

• Instruction access

The stage 1 translation assigns the Normal memory attribute, with the cacheability and

shareability attributes determined by the value of the SCTLR_ELx.I bit for the

translation regime, as follows:

When the value of I is 0

The stage 1 translation assigns the Non-cacheable and Outer Shareable

attributes.

When the value of I is 1

The stage 1 translation assigns the Cacheable, Inner Write-Through

Read-Allocate No Write-Allocate, Outer Write-Through Read-Allocate No

Write-Allocate Outer Shareable attribute.

指令访问依赖于SCTLR.I域

I位为0，表示non-cacheable和outer shareable访问

I位为1，表示cacheable访问。

在开启mmu后可以访问未对齐的指令，但是没有开启mmu的时候，访问没有对齐的指令可能会导致cpu直接挂了。