armv8 mmu 究竟如何选择TTBR0或TTBR1呢？

TTBR的选择(armv8.6手册 2578页)

Selection between TTBR0_ELx and TTBR1_ELx when two VA ranges are supported

Every translation table walk starts by accessing the translation table addressed by the TTBR_ELx for the stage 1

translation for the required translation regime.

For a stage 1 translation that can support two VA ranges, Figure D5-14 shows this VA range split when using 48-bit

VAs, and:

• TTBR0_ELx points to the initial translation table for the lower VA range, that starts at address 0x0000000000000000,

• TTBR1_ELx points to the initial translation table for the upper VA range, that runs up to address 0xFFFFFFFFFFFFFFFF.

As Figure D5-14 shows, for 48-bit VAs:

• The address range translated using TTBR0_ELx is 0x0000000000000000 to 0x0000FFFFFFFFFFFF.

• The address range translated using TTBR1_ELx is 0xFFFF000000000000 to 0xFFFFFFFFFFFFFFFF.

In an implementation that includes ARMv8.2-LVA and is using the 64KB translation granule, for 52-bit VAs:

• The address range translated using TTBR0_ELx is 0x0000000000000000 to 0x000FFFFFFFFFFFFF.

• The address range translated using TTBR1_ELx is 0xFFF0000000000000 to 0xFFFFFFFFFFFFFFFF.

Which TTBR_ELx is used depends only on the VA presented for translation. The most significant bits of the VA

must all be the same value and:

(根据最高位来选择使用TTBR0或者TTRB1)

• If the most significant bits of the VA are zero, then TTBR0_ELx is used.

• If the most significant bits of the VA are one, then TTBR1_ELx is used.

However, it is configurable whether VA[63:56] are considered when determining which TTBR_ELx is used, that is:

• In an implementation that includes ARMv8.2-LVA and is using the 64KB translation granule, whether the

determination depends on VA[63:52] or on VA[55:52].

• Otherwise, whether the determination depends on VA[63:48] or on VA[55:48].

For more information about whether VA[63:56] are considered for this determination see Address tagging in

AArch64 state on page D5-2534.