STM32F103VET6 TIM4_CH4 PWM频率可调，占空比可调

废话不多，直接上代码

void TIM4_Mode_Config(u16 arr, u16 CCR4_Val)
{
    u16 psr = 0;
    GPIO_InitTypeDef GPIO_InitStructure;
    TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
    TIM_OCInitTypeDef  TIM_OCInitStructure;
    
    if(arr < 999)
    {
        psr = 99;
        //Fpwm = 64M / (arr+1) / (psr + 1)
        arr =  64000000 / arr /    100 - 1;
    }
    else
    {
        psr = 0;
        //Fpwm = 64M / (arr+1) / (psr + 1)
        arr =  64000000 / arr - 1;
    }
    //duty circle = CCR4_Val / arr * 100
    CCR4_Val = (CCR4_Val * arr) / 100;
    
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); 
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
    TIM_DeInit(TIM4);
    
    //TIM4-CH4
  GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_9;
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;            
  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
  GPIO_Init(GPIOB, &GPIO_InitStructure);

  TIM_TimeBaseStructure.TIM_Period = arr;      
  TIM_TimeBaseStructure.TIM_Prescaler = psr;      
  TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1 ;    
  TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;  
  TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
  // PWM1 Mode configuration: Channel4 
  TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;       
  TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; 
  TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
  TIM_OCInitStructure.TIM_Pulse = CCR4_Val;    
  TIM_OC4Init(TIM4, &TIM_OCInitStructure);   
  TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
  TIM_ARRPreloadConfig(TIM4, ENABLE);             
  TIM_Cmd(TIM4, ENABLE);                 
}

void SetSysClockTo64Mhz(void)
{
 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC_DeInit();
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
/* Enable HSI */
RCC->CR |= ((uint32_t)RCC_CR_HSION);

/* Wait till HSI is ready and if Time out is reached exit */
do
{
 HSEStatus = RCC->CR & RCC_CR_HSIRDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
{
 HSEStatus = (uint32_t)0x01;
}
else
{
 HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* Enable Prefetch Buffer */
FLASH->ACR |= FLASH_ACR_PRFTBE;
 /* Flash 2 wait state */
 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
 /* HCLK = SYSCLK */
 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */
 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */
 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;

/*  PLL configuration: PLLCLK = HSI/2 * 16 = 64 MHz */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2| RCC_CFGR_PLLMULL16);
 
/* Enable PLL */
 RCC->CR |= RCC_CR_PLLON;
 /* Wait till PLL is ready */
 while((RCC->CR & RCC_CR_PLLRDY) == 0)
 {
 }
 
 /* Select PLL as system clock source */
 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
{
}
}
else
{
}
}

int main(void)
{    
    SetSysClockTo64Mhz();
    TIM4_Mode_Config(10000, 90);
    for(;;)
    {
    }
}