以下内容在stm32f4xx_rcc.h内
- /**
- ******************************************************************************
- * @file stm32f4xx_rcc.h
- * @author MCD Application Team
- * @version V1.5.1
- * @date 22-May-2015
- * @brief This file contains all the functions prototypes for the RCC firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
- /* Define to prevent recursive inclusion -------------------------------------*/
- #ifndef __STM32F4xx_RCC_H
- #define __STM32F4xx_RCC_H
- #ifdef __cplusplus
- extern "C" {
- #endif
- /* Includes ------------------------------------------------------------------*/
- #include "stm32f4xx.h"
- /** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
- /** @addtogroup RCC
- * @{
- */
- /* Exported types ------------------------------------------------------------*/
- typedef struct
- {
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
- }RCC_ClocksTypeDef;
- /* Exported constants --------------------------------------------------------*/
- /** @defgroup RCC_Exported_Constants
- * @{
- */
- /** @defgroup RCC_HSE_configuration
- * @{
- */
- #define RCC_HSE_OFF ((uint8_t)0x00)
- #define RCC_HSE_ON ((uint8_t)0x01)
- #define RCC_HSE_Bypass ((uint8_t)0x05)
- #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
- /**
- * @}
- */
- /** @defgroup RCC_LSE_Dual_Mode_Selection
- * @{
- */
- #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
- #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
- #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \
- ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
- /**
- * @}
- */
- /** @defgroup RCC_PLLSAIDivR_Factor
- * @{
- */
- #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
- #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
- #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
- #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
- #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div4) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div8) ||\
- ((VALUE) == RCC_PLLSAIDivR_Div16))
- /**
- * @}
- */
- /** @defgroup RCC_PLL_Clock_Source
- * @{
- */
- #define RCC_PLLSource_HSI ((uint32_t)0x00000000)
- #define RCC_PLLSource_HSE ((uint32_t)0x00400000)
- #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
- #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
- #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
- #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
- #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
- #if defined(STM32F446xx)
- #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
- #endif /* STM32F446xx */
- #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
- #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
- #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
- #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
- #if defined(STM32F446xx)
- #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
- #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
- #endif /* STM32F446xx */
- #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
- #if defined(STM32F446xx)
- #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
- #endif /* STM32F446xx */
- #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
- #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
- #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
- #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
- /**
- * @}
- */
- /** @defgroup RCC_System_Clock_Source
- * @{
- */
- #if defined(STM32F446xx)
- #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
- #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
- #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
- #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
- #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
- /* Add legacy definition */
- #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
- #endif /* STM32F446xx */
- #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
- #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
- #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
- #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
- #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
- #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
- /**
- * @}
- */
- /** @defgroup RCC_AHB_Clock_Source
- * @{
- */
- #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
- #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
- #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)