乘法器的verilog实现

https://www.cnblogs.com/shengansong/archive/2011/05/23/2054401.html

一、对两个二进制数进行相乘运算，运用列式求法我们可以得知，乘法最终就是由加法和移位运算构成的，由此可以用高速度的加法和移位实现乘法操作，具体代码如下：

 

module multi_4bits_pipelining(mul_a, mul_b, clk, rst_n, mul_out);
    
    input [3:0] mul_a, mul_b;
    input       clk;
    input       rst_n;
    output [7:0] mul_out;

    reg [7:0] mul_out;

    reg [7:0] stored0;
    reg [7:0] stored1;
    reg [7:0] stored2;
    reg [7:0] stored3;

    reg [7:0] add01;
    reg [7:0] add23;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            mul_out <= 0;
            stored0 <= 0;
            stored1 <= 0;
            stored2 <= 0;
            stored3 <= 0;
            add01 <= 0;
            add23 <= 0;
        end
        else begin
            stored0 <= mul_b[0]? {4'b0, mul_a} : 8'b0;
            stored1 <= mul_b[1]? {3'b0, mul_a, 1'b0} : 8'b0;
            stored2 <= mul_b[2]? {2'b0, mul_a, 2'b0} : 8'b0;
            stored3 <= mul_b[3]? {1'b0, mul_a, 3'b0} : 8'b0;

            add01 <= stored1 + stored0;
            add23 <= stored3 + stored2;

            mul_out <= add01 + add23;
        end
    end

endmodule

module mult(
    input clk,
    input [3:0]a,b,
    input rst_n,
    output [7:0] out);

wire [5:0]out1;
wire [7:0]out2;
reg [6:0]temp3;
reg [5:0]temp2;
reg [4:0]temp1;
reg [3:0]temp0;
function [3:0]mult4;
input [3:0]operand;
input sel;
mult4=(sel)?operand:4'b0000;  
endfunction
 
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
    temp0<=0;
    temp1<=0;
    temp2<=0;
    temp3<=0;
    end
else
begin
    temp0<=mult4(a,b[0]);
    temp1<=mult4(a,b[1])<<1;
    temp2<=mult4(a,b[2])<<2;
    temp3<=mult4(a,b[3])<<3;
end
assign out1=temp0+temp1;
assign out2=temp2+temp3;
assign out=out1+out2;
endmodule