FIRRTL specification 2020Oct edition翻译之第一章第二章

1 Introduction
1.1 Background
The ideas for FIRRTL (Flexible Intermediate Representation for RTL) originated from work on Chisel, a hardware description language (HDL) embedded in Scala used for writing highly-parameterized circuit design generators.
Chisel designers manipulate circuit components using Scala functions, encode
their interfaces in Scala types, and use Scala’s object-orientation features to
write their own circuit libraries. This form of meta-programming enables
expressive, reliable and type-safe generators that improve RTL design productivity and robustness.
The computer architecture research group at U.C. Berkeley relies critically on Chisel to allow small teams of graduate students to design sophisticated RTL circuits. Over a three year period with under twelve graduate
students, the architecture group has taped-out over ten different designs.
Internally, the investment in developing and learning Chisel was rewarded
with huge gains in productivity. However, Chisel’s external rate of adoption
was slow for the following reasons.
1. Writing custom circuit transformers requires intimate knowledge about
the internals of the Chisel compiler.
2. Chisel semantics are under-specified and thus impossible to target from
other languages.
3. Error checking is unprincipled due to under-specified semantics resulting in incomprehensible error messages.
4. Learning a functional programming language (Scala) is difficult for RTL
designers with limited programming language experience.
5. Confounding the previous point, conceptually separating the embedded
Chisel HDL from the host language is difficult for new users.
6. The output of Chisel (Verilog) is unreadable and slow to simulate.
As a consequence, Chisel needed to be redesigned from the ground up
to standardize its semantics, modularize its compilation process, and cleanly
separate its front-end, intermediate representation, and backends. A well
defined intermediate representation (IR) allows the system to be targeted
by other HDLs embedded in other host programming languages, making it
possible for RTL designers to work within a language they are already comfortable with. A clearly defined IR with a concrete syntax also allows for
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Specification for the FIRRTL Language Version 0.2.0
inspection of the output of circuit generators and transformers thus making
clear the distinction between the host language and the constructed circuit.
Clearly defined semantics allows users without knowledge of the compiler
implementation to write circuit transformers; examples include optimization
of circuits for simulation speed, and automatic insertion of signal activity
counters. An additional benefit of a well defined IR is the structural invariants that can be enforced before and after each compilation stage, resulting
in a more robust compiler and structured mechanism for error checking.
1.2 Design Philosophy
FIRRTL represents the standardized elaborated circuit that the Chisel HDL
produces. FIRRTL represents the circuit immediately after Chisel’s elaboration but before any circuit simplification. It is designed to resemble the Chisel
HDL after all meta-programming has executed. Thus, a user program that
makes little use of meta-programming facilities should look almost identical
to the generated FIRRTL.
For this reason, FIRRTL has first-class support for high-level constructs
such as vector types, bundle types, conditional statements, partial connects,
and modules. These high-level constructs are then gradually removed by a
sequence of lowering transformations. During each lowering transformation,
the circuit is rewritten into an equivalent circuit using simpler, lower-level
constructs. Eventually the circuit is simplified to its most restricted form,
resembling a structured netlist, which allows for easy translation to an output language (e.g. Verilog). This form is given the name lowered FIRRTL
(LoFIRRTL) and is a strict subset of the full FIRRTL language.
Because the host language is now used solely for its meta-programming
facilities, the frontend can be very light-weight, and additional HDLs written
in other languages can target FIRRTL and reuse the majority of the compiler
toolchain.
2 Acknowledgments
The FIRRTL language could not have been developed without the help of
many of the faculty and students in the ASPIRE lab, and the University of
California, Berkeley.
This project originated from discussions with the authors’ advisor, Jonathan
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Specification for the FIRRTL Language Version 0.2.0
Bachrach, who indicated the need for a structural redesign of the Chisel system around a well-defined intermediate representation. Patrick Li designed
and implemented the first prototype of the FIRRTL language, wrote the initial specification for the language, and presented it to the Chisel group consisting of Adam Izraelevitz, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, Donggyu Kim, Jack Koenig, Martin Maas,
Albert Magyar, Colin Schmidt, Andrew Waterman, Yunsup Lee, Richard
Lin, Eric Love, Albert Ou, Stephen Twigg, John Bachan, David Donofrio,
Farzad Fatollahi-Fard, Jim Lawson, Brian Richards, Krste Asanovi´c, and
John Wawrzynek.
Adam Izraelevitz then reworked the design and re-implemented FIRRTL,
and after many discussions with Patrick Li and the Chisel group, refined the
design to its present version.
The authors would like to thank the following individuals in particular
for their contributions to the FIRRTL project:
• Andrew Waterman: for his many contributions to the design of FIRRTL’s constructs, for his work on Chisel 3.0, and for porting architecture research infrastructure
• Richard Lin: for improving the Chisel 3.0 code base for release quality
• Jack Koenig: for implementing the FIRRTL parser in Scala
• Henry Cook: for porting and cleaning up many aspects of Chisel 3.0,
including the testing infrastructure and the parameterization library
• Chick Markley: for creating the new testing harness and porting the
Chisel tutorial
• Stephen Twigg: for his expertise in hardware intermediate representations and for providing many corner cases to consider
• Palmer Dabbelt, Eric Love, Martin Maas, Christopher Celio, and Scott
Beamer: for their feedback on previous drafts of the FIRRTL specification
And finally this project would not have been possible without the continuous feedback and encouragement of Jonathan Bachrach, and his leadership
on and implementation of Chisel.
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Specification for the FIRRTL Language Version 0.2.0
This research was partially funded by DARPA Award Number HR0011-
12-2-0016, the Center for Future Architecture Research, a member of STARnet, a Semiconductor Research Corporation program sponsored by MARCO
and DARPA, and ASPIRE Lab industrial sponsors and affiliates Intel, Google,
Huawei, Nokia, NVIDIA, Oracle, and Samsung. Any opinions, findings, conclusions, or recommendations in this paper are solely those of the authors
and does not necessarily reflect the position or the policy of the sponsors.