firrtl

最新推荐文章于 2024-07-15 14:39:44 发布

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最新推荐文章于 2024-07-15 14:39:44 发布

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文章标签： java 开发工具操作系统

原文链接：https://my.oschina.net/u/2963604/blog/1832576

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2019独角兽企业重金招聘Python工程师标准>>>

动手---sbt(2)之后，再回头看 chisel第一个实验，根据 https://github.com/freechipsproject/firrtl 发现firrtl没有执行sbt assembly命令，重新执行这个命令，结果成功。如下图：

joe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ sbt assembly
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/project
[info] Loading settings from build.sbt ...
[info] Set current project to firrtl (in build file:/media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/)
[info] Including: nscala-time_2.11-2.14.0.jar
[info] Including: slf4j-api-1.7.25.jar
[info] Including: json4s-core_2.11-3.5.3.jar
[info] Including: logback-classic-1.2.3.jar
[info] Including: scala-library-2.11.12.jar
[info] Including: joda-time-2.9.4.jar
[info] Including: logback-core-1.2.3.jar
[info] Including: json4s-ast_2.11-3.5.3.jar
[info] Including: joda-convert-1.2.jar
[info] Including: snakeyaml-1.17.jar
[info] Including: scopt_2.11-3.6.0.jar
[info] Including: json4s-scalap_2.11-3.5.3.jar
[info] Including: moultingyaml_2.11-0.4.0.jar
[info] Including: json4s-native_2.11-3.5.3.jar
[info] Including: scala-reflect-2.11.12.jar
[info] Including: paranamer-2.8.jar
[info] Including: scala-xml_2.11-1.0.6.jar
[info] Including: antlr4-runtime-4.7.jar
[info] Including: scala-logging_2.11-3.7.2.jar
[info] Checking every *.class/*.jar file's SHA-1.
[info] Merging files...
[warn] Merging 'META-INF/NOTICE.txt' with strategy 'rename'
[warn] Merging 'META-INF/LICENSE.txt' with strategy 'rename'
[warn] Merging 'META-INF/MANIFEST.MF' with strategy 'discard'
[warn] Merging 'META-INF/maven/ch.qos.logback/logback-classic/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/ch.qos.logback/logback-classic/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/ch.qos.logback/logback-core/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/ch.qos.logback/logback-core/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/com.thoughtworks.paranamer/paranamer/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/com.thoughtworks.paranamer/paranamer/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/joda-time/joda-time/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/joda-time/joda-time/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.antlr/antlr4-runtime/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.antlr/antlr4-runtime/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.joda/joda-convert/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.joda/joda-convert/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.slf4j/slf4j-api/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.slf4j/slf4j-api/pom.xml' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.yaml/snakeyaml/pom.properties' with strategy 'discard'
[warn] Merging 'META-INF/maven/org.yaml/snakeyaml/pom.xml' with strategy 'discard'
[warn] Strategy 'discard' was applied to 17 files
[warn] Strategy 'rename' was applied to 2 files
[info] SHA-1: d20bcaa38fa32c07d42993a42ddbb09b3a8c7b21
[info] Packaging /media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/./utils/bin/firrtl.jar ...
[info] Done packaging.
[success] Total time: 7 s, completed Jun 20, 2018 9:33:12 AM

但执行 sbt publish-local命令出錯

joe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ sbt publish-local
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/project
[info] Loading settings from build.sbt ...
[info] Set current project to firrtl (in build file:/media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/)
[error] Not a valid command: publish-local
[error] Not a valid project ID: publish-local
[error] Expected ':'
[error] Not a valid key: publish-local (similar: publishLocal, publishTo, publish)
[error] publish-local
[error]              ^

然后我根据上面网址的说明，执行测试操作：

joe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ sbt "testOnly firrtlTests.UnitTests"
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/project
[info] Loading settings from build.sbt ...
[info] Set current project to firrtl (in build file:/media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/)
Total FIRRTL Compile Time: 20.8 ms
[info] UnitTests:
[info] Pull muxes
[info] - should not be exponential in runtime
[info] Connecting bundles of different types
[info] - should throw an exception
[info] Initializing a register with a different type
[info] - should throw an exception
[info] Partial connection two bundle types whose relative flips don't match but leaf node directions do
[info] - should connect correctly
[info] Emitting a nested expression
[info] - should throw an exception
[info] After splitting, emitting a nested expression
[info] - should compile
[info] Simple compound expressions
[info] - should be split
[info] Smaller widths
[info] - should be explicitly padded
[info] Indexes into sub-accesses
[info] - should be dealt with
[info] Oversized bit select
[info] - should throw an exception
[info] Oversized head select
[info] - should throw an exception
[info] Oversized tail select
[info] - should throw an exception
[info] Partial connecting incompatable types
[info] - should throw an exception
[info] Conditional connection of clocks
[info] - should throw an exception
[info] Parsing SInts
[info] - should work
[info] Verilog SInts
[info] - should work
[info] Out of bound accesses
[info] - should be invalid
[info] ScalaTest
[info] Run completed in 1 second, 420 milliseconds.
[info] Total number of tests run: 17
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 17, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[info] Passed: Total 17, Failed 0, Errors 0, Passed 17
[success] Total time: 4 s, completed Jun 20, 2018 9:43:22 AM

再执行sbt ~compile,一直出再下面的等待：

joe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ sbt ~compile
[info] Loading settings from plugins.sbt ...
[info] Loading project definition from /media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/project
[info] Loading settings from build.sbt ...
[info] Set current project to firrtl (in build file:/media/46bb100d-2505-4025-8425-34ecf3129209/download/firrtl/firrtl/)
[success] Total time: 1 s, completed Jun 20, 2018 9:46:18 AM
1. Waiting for source changes... (press enter to interrupt)

我只好中断了。

此时，根据firrtl目录中的readme文件说明（不要再参考https://github.com/freechipsproject/firrtl），执行：

joe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ ./utils/bin/firrtl -td regress -tn rocket --custom-transforms tutorial.lesson1.AnalyzeCircuit
------------------------------------------------------------------------------
Error: Input file regress/rocket.fir not found
------------------------------------------------------------------------------
Usage: firrtl [options] [<arg>...]

common options
  -tn, --top-name <top-level-circuit-name>
                           This options defines the top level circuit, defaults to dut when possible
  -td, --target-dir <target-directory>
                           This options defines a work directory for intermediate files, default is .
  -ll, --log-level <Error|Warn|Info|Debug|Trace>
                           This options defines a work directory for intermediate files, default is .
  -cll, --class-log-level <FullClassName:[Error|Warn|Info|Debug|Trace]>[,...]
                           This options defines a work directory for intermediate files, default is .
  -ltf, --log-to-file      default logs to stdout, this flags writes to topName.log or firrtl.log if no topName
  -lcn, --log-class-names  shows class names and log level in logging output, useful for target --class-log-level
  --help                   prints this usage text
  <arg>...                 optional unbounded args
firrtl options
  -i, --input-file <firrtl-source>
                           use this to override the default input file name , default is empty
  -o, --output-file <output>
                           use this to override the default output file name, default is empty
  -faf, --annotation-file <input-anno-file>
                           Used to specify annotation files (can appear multiple times)
  -foaf, --output-annotation-file <output-anno-file>
                           use this to set the annotation output file
  -X, --compiler <high|middle|low|verilog|sverilog>
                           compiler to use, default is verilog
  --info-mode <ignore|use|gen|append>
                           specifies the source info handling, default is append
  -fct, --custom-transforms <package>.<class>
                           runs these custom transforms during compilation.
  -fil, --inline <circuit>[.<module>[.<instance>]][,..],
                           Inline one or more module (comma separated, no spaces) module looks like "MyModule" or "MyModule.myinstance
  -firw, --infer-rw <circuit>
                           Enable readwrite port inference for the target circuit
  -frsq, --repl-seq-mem -c:<circuit>:-i:<filename>:-o:<filename>
                           Replace sequential memories with blackboxes + configuration file
  -clks, --list-clocks -c:<circuit>:-m:<module>:-o:<filename>
                           List which signal drives each clock of every descendent of specified module
  -fsm, --split-modules    Emit each module to its own file in the target directory.
  --no-check-comb-loops    Do NOT check for combinational loops (not recommended)
  --no-dce                 Do NOT run dead code elimination

既然出现问题，那就再回头参考 https://github.com/freechipsproject/firrtl 中说明：

oe@joe-Aspire-Z3730:/media/sdb4/download/firrtl/firrtl$ utils/bin/firrtl -i regress/rocket.fir -o regress/rocket.v -X verilog
------------------------------------------------------------------------------
Error: Input file regress/rocket.fir not found
------------------------------------------------------------------------------
Usage: firrtl [options] [<arg>...]

这说明，还是有问题。

发现 https://www.e-learn.cn/content/wangluowenzhang/186199 这个帖子有解决方法，并且提到 https://github.com/ucb-bar/chisel-template 教程

（以前的Max2目录下有测试代码），执行如下命令：

joe@joe-Aspire-Z3730:/media/sdb4/download/scala/chiseltest/chisel_max$ ls
build.sbt  max2.scala  project  target  test_run_dir
joe@joe-Aspire-Z3730:/media/sdb4/download/scala/chiseltest/chisel_max$ sbt "runMain Hellp"
[info] Loading project definition from /media/46bb100d-2505-4025-8425-34ecf3129209/download/scala/chiseltest/chisel_max/project
[info] Loading settings from build.sbt ...
[info] Set current project to chisel-tutorial (in build file:/media/46bb100d-2505-4025-8425-34ecf3129209/download/scala/chiseltest/chisel_max/)
[info] Running Hellp 
Error: Unknown option --backend
Error: Unknown option --compile
Try --help for more information.
[success] Total time: 3 s, completed Jun 20, 2018 10:34:03 AM

虽然成功了，但是还是没有发现.v文件。估计是不是要用到firrtl命令。

转载于:https://my.oschina.net/u/2963604/blog/1832576