嵌入式linux开发笔记: 串口

最新推荐文章于 2022-03-23 22:03:08 发布
最新推荐文章于 2022-03-23 22:03:08 发布
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分类专栏： Linux
版权声明：本文为博主原创文章，遵循 CC 4.0 BY 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/f2157120/article/details/103760377
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1> led.c

#include "s3c2440_soc.h"

void delay(volatile int d)
{
	while (d--);
}

int led_test(void)
{
	int val = 0;  /* val: 0b000, 0b111 */
	int tmp;

	/* 设置GPFCON让GPF4/5/6配置为输出引脚 */
	GPFCON &= ~((3<<8) | (3<<10) | (3<<12));
	GPFCON |=  ((1<<8) | (1<<10) | (1<<12));

	/* 循环点亮 */
	while (1)
	{
		tmp = ~val;
		tmp &= 7;
		GPFDAT &= ~(7<<4);
		GPFDAT |= (tmp<<4);
		delay(100000);
		val++;
		if (val == 8)
			val =0;
		
	}

	return 0;
}

 2> main.c

#include "s3c2440_soc.h"
#include "uart.h"

int main(void)
{
	unsigned char c;
	
	uart0_init();
	puts("Hello, world!\n\r");
	
	while(1)
	{
		c = getchar();
		if (c == '\r')
		{
			putchar('\n');
		}

		if (c == '\n')
		{
			putchar('\r');
		}

		putchar(c);
	}
	return 0;
}

3> s3c2440_soc.h

/*
制  作:www.100ask.org深圳百问网科技有限公司
工程师：韦东山
当前版本：v1.0
*/

#ifndef  __S3C2440_SOC_H
#define  __S3C2440_SOC_H

#define     __REG(x)					(*(volatile unsigned int *)(x)) 
#define     __REG_BYTE(x)				(*(volatile unsigned char *)(x)) 

/*Memory Controllers*/
#define     BWSCON                   __REG(0x48000000)   //Bus width & wait status control   
#define     BANKCON0                 __REG(0x48000004)   //Boot ROM control                  
#define     BANKCON1                 __REG(0x48000008)   //BANK1 control                     
#define     BANKCON2                 __REG(0x4800000C)   //BANK2 control                     
#define     BANKCON3                 __REG(0x48000010)   //BANK3 control                     
#define     BANKCON4                 __REG(0x48000014)   //BANK4 control                     
#define     BANKCON5                 __REG(0x48000018)   //BANK5 control                     
#define     BANKCON6                 __REG(0x4800001C)   //BANK6 control                     
#define     BANKCON7                 __REG(0x48000020)   //BANK7 control                     
#define     REFRESH                  __REG(0x48000024)   //DRAM/SDRAM refresh control        
#define     BANKSIZE                 __REG(0x48000028)   //Flexible bank size                
#define     MRSRB6                   __REG(0x4800002C)   //Mode register set for SDRAM BANK6 
#define     MRSRB7                   __REG(0x48000030)   //Mode register set for SDRAM BANK7 

/*USB Host Controller*/ 
#define     HcRevision               __REG(0x49000000)
#define     HcControl                __REG(0x49000004)
#define     HcCommonStatus           __REG(0x49000008)
#define     HcInterruptStatus        __REG(0x4900000C)
#define     HcInterruptEnable        __REG(0x49000010)
#define     HcInterruptDisable       __REG(0x49000014)
#define     HcHCCA                   __REG(0x49000018)
#define     HcPeriodCuttentED        __REG(0x4900001C)
#define     HcControlHeadED          __REG(0x49000020)
#define     HcControlCurrentED       __REG(0x49000024)
#define     HcBulkHeadED             __REG(0x49000028)
#define     HcBulkCurrentED          __REG(0x4900002C)
#define     HcDoneHead               __REG(0x49000030)
#define     HcRmInterval             __REG(0x49000034)
#define     HcFmRemaining            __REG(0x49000038)
#define     HcFmNumber               __REG(0x4900003C)
#define     HcPeriodicStart          __REG(0x49000040)
#define     HcLSThreshold            __REG(0x49000044)
#define     HcRhDescriptorA          __REG(0x49000048)
#define     HcRhDescriptorB          __REG(0x4900004C)
#define     HcRhStatus               __REG(0x49000050)
#define     HcRhPortStatus1          __REG(0x49000054)
#define     HcRhPortStatus2          __REG(0x49000058)

/*Interrupt Controller*/
#define     SRCPND                   __REG(0X4A000000)  //Interrupt request status       
#define     INTMOD                   __REG(0X4A000004)  //Interrupt mode control         
#define     INTMSK                   __REG(0X4A000008)  //Interrupt mask control         
#define     PRIORITY                 __REG(0X4A00000C)  //IRQ priority control           
#define     INTPND                   __REG(0X4A000010)  //Interrupt request status       
#define     INTOFFSET                __REG(0X4A000014)  //Interrupt request source offset
#define     SUBSRCPND                __REG(0X4A000018)  //Sub source pending             
#define     INTSUBMSK                __REG(0X4A00001C)  //Interrupt sub mask    
    
/*DMA*/ 
#define     DISRC0                   __REG(0x4B000000)  //DMA 0 initial source              
#define     DISRCC0                  __REG(0x4B000004)  //DMA 0 initial source control      
#define     DIDST0                   __REG(0x4B000008)  //DMA 0 initial destination         
#define     DIDSTC0                  __REG(0x4B00000C)  //DMA 0 initial destination control 
#define     DCON0                    __REG(0x4B000010)  //DMA 0 control                     
#define     DSTAT0                   __REG(0x4B000014)  //DMA 0 count                       
#define     DCSRC0                   __REG(0x4B000018)  //DMA 0 current source              
#define     DCDST0                   __REG(0x4B00001C)  //DMA 0 current destination         
#define     DMASKTRIG0               __REG(0x4B000020)  //DMA 0 mask trigger                
#define     DISRC1                   __REG(0x4B000040)  //DMA 1 initial source              
#define     DISRCC1                  __REG(0x4B000044)  //DMA 1 initial source control      
#define     DIDST1                   __REG(0x4B000048)  //DMA 1 initial destination         
#define     DIDSTC1                  __REG(0x4B00004C)  //DMA 1 initial destination control 
#define     DCON1                    __REG(0x4B000050)  //DMA 1 control                     
#define     DSTAT1                   __REG(0x4B000054)  //DMA 1 count                       
#define     DCSRC1                   __REG(0x4B000058)  //DMA 1 current source              
#define     DCDST1                   __REG(0x4B00005C)  //DMA 1 current destination         
#define     DMASKTRIG1               __REG(0x4B000060)  //DMA 1 mask trigger                
#define     DISRC2                   __REG(0x4B000080)  //DMA 2 initial source              
#define     DISRCC2                  __REG(0x4B000084)  //DMA 2 initial source control      
#define     DIDST2                   __REG(0x4B000088)  //DMA 2 initial destination         
#define     DIDSTC2                  __REG(0x4B00008C)  //DMA 2 initial destination control 
#define     DCON2                    __REG(0x4B000090)  //DMA 2 control                     
#define     DSTAT2                   __REG(0x4B000094)  //DMA 2 count                       
#define     DCSRC2                   __REG(0x4B000098)  //DMA 2 current source              
#define     DCDST2                   __REG(0x4B00009C)  //DMA 2 current destination         
#define     DMASKTRIG2               __REG(0x4B0000A0)  //DMA 2 mask trigger                
#define     DISRC3                   __REG(0x4B0000C0)  //DMA 3 initial source              
#define     DISRCC3                  __REG(0x4B0000C4)  //DMA 3 initial source control      
#define     DIDST3                   __REG(0x4B0000C8)  //DMA 3 initial destination         
#define     DIDSTC3                  __REG(0x4B0000CC)  //DMA 3 initial destination control 
#define     DCON3                    __REG(0x4B0000D0)  //DMA 3 control                     
#define     DSTAT3                   __REG(0x4B0000D4)  //DMA 3 count                       
#define     DCSRC3                   __REG(0x4B0000D8)  //DMA 3 current source              
#define     DCDST3                   __REG(0x4B0000DC)  //DMA 3 current destination         
#define     DMASKTRIG3               __REG(0x4B0000E0)  //DMA 3 mask trigger     

/*Clock & Power Management*/
#define     LOCKTIME                 __REG(0x4C000000)  //PLL lock time counter         
#define     MPLLCON                  __REG(0x4C000004)  //MPLL control                  
#define     UPLLCON                  __REG(0x4C000008)  //UPLL control                  
#define     CLKCON                   __REG(0x4C00000C)  //Clock generator control       
#define     CLKSLOW                  __REG(0x4C000010)  //Slow clock control            
#define     CLKDIVN                  __REG(0x4C000014)  //Clock divider control         
#define     CAMDIVN                  __REG(0x4C000018)  //Camera clock divider control  

/*LCD Controller*/
#define	    LCDCON1  	             __REG(0X4D000000)  //LCD control 1                          
#define	    LCDCON2  	             __REG(0X4D000004)  //LCD control 2                          
#define	    LCDCON3  	             __REG(0X4D000008)  //LCD control 3                          
#define	    LCDCON4  	             __REG(0X4D00000C)  //LCD control 4                          
#define	    LCDCON5  	             __REG(0X4D000010)  //LCD control 5                          
#define	    LCDSADDR1	             __REG(0X4D000014)  //STN/TFT: frame buffer start address 1  
#define	    LCDSADDR2	             __REG(0X4D000018)  //STN/TFT: frame buffer start address 2  
#define	    LCDSADDR3	             __REG(0X4D00001C)  //STN/TFT: virtual screen address set    
#define	    REDLUT   	             __REG(0X4D000020)  //STN: red lookup table                  
#define	    GREENLUT 	             __REG(0X4D000024)  //STN: green lookup table                
#define	    BLUELUT  	             __REG(0X4D000028)  //STN: blue lookup table                 
#define	    DITHMODE 	             __REG(0X4D00004C)  //STN: dithering mode                    
#define	    TPAL     	             __REG(0X4D000050)  //TFT: temporary palette                 
#define	    LCDINTPND	             __REG(0X4D000054)  //LCD interrupt pending                  
#define	    LCDSRCPND	             __REG(0X4D000058)  //LCD interrupt source                   
#define	    LCDINTMSK	             __REG(0X4D00005C)  //LCD interrupt mask                     
#define	    TCONSEL  	             __REG(0X4D000060)  //TCON(LPC3600/LCC3600) control    

/*NAND Flash*/

#define     NFCONF                   __REG(0x4E000000)  //NAND flash configuration             
#define     NFCONT                   __REG(0x4E000004)  //NAND flash control                   
#define     NFCMD                    __REG(0x4E000008)  //NAND flash command                   
#define     NFADDR                   __REG(0x4E00000C)  //NAND flash address                   
#define     NFDATA                   __REG(0x4E000010)  //NAND flash data                      
#define     NFMECC0                  __REG(0x4E000014)  //NAND flash main area ECC0/1          
#define     NFMECC1                  __REG(0x4E000018)  //NAND flash main area ECC2/3          
#define     NFSECC                   __REG(0x4E00001C)  //NAND flash spare area ECC            
#define     NFSTAT                   __REG(0x4E000020)  //NAND flash operation status          
#define     NFESTAT0                 __REG(0x4E000024)  //NAND flash ECC status for I/O[7:0]   
#define     NFESTAT1                 __REG(0x4E000028)  //NAND flash ECC status for I/O[15:8]  
#define     NFMECC0_STATUS           __REG(0x4E00002C)  //NAND flash main area ECC0 status     
#define     NFMECC1_STATUS           __REG(0x4E000030)  //NAND flash main area ECC1 status     
#define     NFSECC_STATUS            __REG(0x4E000034)  //NAND flash spare area ECC status     
#define     NFSBLK                   __REG(0x4E000038)  //NAND flash start block address       
#define     NFEBLK                   __REG(0x4E00003C)  //NAND flash end block address       

/*Camera Interface*/
#define     CISRCFMT                 __REG(0x4F000000)  //Input source format                                
#define     CIWDOFST                 __REG(0x4F000004)  //Window offset register                             
#define     CIGCTRL                  __REG(0x4F000008)  //Global control register                            
#define     CICOYSA1                 __REG(0x4F000018)  //Y 1st frame start address for codec DMA            
#define     CICOYSA2                 __REG(0x4F00001C)  //Y 2nd frame start address for codec DMA            
#define     CICOYSA3                 __REG(0x4F000020)  //Y 3nd frame start address for codec DMA            
#define     CICOYSA4                 __REG(0x4F000024)  //Y 4th frame start address for codec DMA            
#define     CICOCBSA1                __REG(0x4F000028)  //Cb 1st frame start address for codec DMA           
#define     CICOCBSA2                __REG(0x4F00002C)  //Cb 2nd frame start address for codec DMA           
#define     CICOCBSA3                __REG(0x4F000030)  //Cb 3nd frame start address for codec DMA           
#define     CICOCBSA4                __REG(0x4F000034)  //Cb 4th frame start address for codec DMA           
#define     CICOCRSA1                __REG(0x4F000038)  //Cr 1st frame start address for codec DMA           
#define     CICOCRSA2                __REG(0x4F00003C)  //Cr 2nd frame start address for codec DMA           
#define     CICOCRSA3                __REG(0x4F000040)  //Cr 3nd frame start address for codec DMA           
#define     CICOCRSA4                __REG(0x4F000044)  //Cr 4th frame start address for codec DMA           
#define     CICOTRGFMT               __REG(0x4F000048)  //Target image format of codec DMA                   
#define     CICOCTRL                 __REG(0x4F00004C)  //Codec DMA control related                          
#define     CICOSCPRERATIO           __REG(0x4F000050)  //Codec pre-scaler ratio control                     
#define     CICOSCPREDST             __REG(0x4F000054)  //Codec pre-scaler destination format                
#define     CICOSCCTRL               __REG(0x4F000058)  //Codec main-scaler control                          
#define     CICOTAREA                __REG(0x4F00005C)  //Codec scaler target area                           
#define     CICOSTATUS               __REG(0x4F000064)  //Codec path status                                  
#define     CIPRCLRSA1               __REG(0x4F00006C)  //RGB 1st frame start address for preview DMA        
#define     CIPRCLRSA2               __REG(0x4F000070)  //RGB 2nd frame start address for preview DMA        
#define     CIPRCLRSA3               __REG(0x4F000074)  //RGB 3nd frame start address for preview DMA        
#define     CIPRCLRSA4               __REG(0x4F000078)  //RGB 4th frame start address for preview DMA        
#define     CIPRTRGFMT               __REG(0x4F00007C)  //Target image format of preview DMA                 
#define     CIPRCTRL                 __REG(0x4F000080)  //Preview DMA control related                        
#define     CIPRSCPRERATIO           __REG(0x4F000084)  //Preview pre-scaler ratio control                   
#define     CIPRSCPREDST             __REG(0x4F000088)  //Preview pre-scaler destination format              
#define     CIPRSCCTRL               __REG(0x4F00008C)  //Preview main-scaler control                        
#define     CIPRTAREA                __REG(0x4F000090)  //Preview scaler target area                         
#define     CIPRSTATUS               __REG(0x4F000098)  //Preview path status                                
#define     CIIMGCPT                 __REG(0x4F0000A0)  //Image capture enable command       

/*UART*/
#define     ULCON0                   __REG(0x50000000)  //UART 0 line control      
#define     UCON0                    __REG(0x50000004)  //UART 0 control           
#define     UFCON0                   __REG(0x50000008)  //UART 0 FIFO control      
#define     UMCON0                   __REG(0x5000000C)  //UART 0 modem control     
#define     UTRSTAT0                 __REG(0x50000010)  //UART 0 Tx/Rx status      
#define     UERSTAT0                 __REG(0x50000014)  //UART 0 Rx error status   
#define     UFSTAT0                  __REG(0x50000018)  //UART 0 FIFO status       
#define     UMSTAT0                  __REG(0x5000001C)  //UART 0 modem status    
#define     UTXH0                    __REG_BYTE(0x50000020)  //UART 0 transmission hold 
#define     URXH0                    __REG_BYTE(0x50000024)  //UART 0 receive buffer    
#define     UBRDIV0                  __REG(0x50000028)  //UART 0 baud rate divisor 
#define     ULCON1                   __REG(0x50004000)  //UART 1 line control      
#define     UCON1                    __REG(0x50004004)  //UART 1 control           
#define     UFCON1                   __REG(0x50004008)  //UART 1 FIFO control      
#define     UMCON1                   __REG(0x5000400C)  //UART 1 modem control     
#define     UTRSTAT1                 __REG(0x50004010)  //UART 1 Tx/Rx status      
#define     UERSTAT1                 __REG(0x50004014)  //UART 1 Rx error status   
#define     UFSTAT1                  __REG(0x50004018)  //UART 1 FIFO status       
#define     UMSTAT1                  __REG(0x5000401C)  //UART 1 modem status        
#define     UTXH1                    __REG(0x50004020)  //UART 1 transmission hold 
#define     URXH1                    __REG(0x50004024)  //UART 1 receive buffer   
#define     UBRDIV1                  __REG(0x50004028)  //UART 1 baud rate divisor 
#define     ULCON2                   __REG(0x50008000)  //UART 2 line control      
#define     UCON2                    __REG(0x50008004)  //UART 2 control           
#define     UFCON2                   __REG(0x50008008)  //UART 2 FIFO control       
#define     UTRSTAT2                 __REG(0x50008010)  //UART 2 Tx/Rx status      
#define     UERSTAT2                 __REG(0x50008014)  //UART 2 Rx error status   
#define     UFSTAT2                  __REG(0x50008018)  //UART 2 FIFO status       
#define     UTXH2                    __REG(0x50008020)  //UART 2 transmission hold 
#define     URXH2                    __REG(0x50008024)  //UART 2 receive buffer     
#define     UBRDIV2                  __REG(0x50008028)  //UART 2 baud rate divisor 

/*PWM Timer*/                  
#define     TCFG0                    __REG(0x51000000)  //Timer configuration         
#define     TCFG1                    __REG(0x51000004)  //Timer configuration         
#define     TCON                     __REG(0x51000008)  //Timer control               
#define     TCNTB0                   __REG(0x5100000C)  //Timer count buffer 0        
#define     TCMPB0                   __REG(0x51000010)  //Timer compare buffer 0      
#define     TCNTO0                   __REG(0x51000014)  //Timer count observation 0   
#define     TCNTB1                   __REG(0x51000018)  //Timer count buffer 1        
#define     TCMPB1                   __REG(0x5100001C)  //Timer compare buffer 1      
#define     TCNTO1                   __REG(0x51000020)  //Timer count observation 1   
#define     TCNTB2                   __REG(0x51000024)  //Timer count buffer 2        
#define     TCMPB2                   __REG(0x51000028)  //Timer compare buffer 2      
#define     TCNTO2                   __REG(0x5100002C)  //Timer count observation 2   
#define     TCNTB3                   __REG(0x51000030)  //Timer count buffer 3        
#define     TCMPB3                   __REG(0x51000034)  //Timer compare buffer 3      
#define     TCNTO3                   __REG(0x51000038)  //Timer count observation 3   
#define     TCNTB4                   __REG(0x5100003C)  //Timer count buffer 4        
#define     TCNTO4                   __REG(0x51000040)  //Timer count observation 4  

/*USB Device*/  
#define     FUNC_ADDR_REG            __REG(0x52000140)  //Function address                            
#define     PWR_REG                  __REG(0x52000144)  //Power management                            
#define     EP_INT_REG               __REG(0x52000148)  //interrupt pending and clear                 
#define     USB_INT_REG              __REG(0x52000158)  //USB interrupt pending and clear             
#define     EP_INT_EN_REG            __REG(0x5200015C)  //Interrupt enable                            
#define     USB_INT_EN_REG           __REG(0x5200016C)  //Interrupt enable                            
#define     FRAME_NUM1_REG           __REG(0x52000170)  //Frame number lower byte                     
#define     FRAME_NUM2_REG           __REG(0x52000174)  //Frame number higher byte                    
#define     INDEX_REG                __REG(0x52000178)  //Register index                              
#define     EP0_CSR                  __REG(0x52000184)  //Endpoint 0 status                           
#define     IN_CSR1_REG              __REG(0x52000184)  //In endpoint control status                  
#define     IN_CSR2_REG              __REG(0x52000188)  //In endpoint control status                  
#define     MAXP_REG                 __REG(0x52000180)  //Endpoint max packet                         
#define     OUT_CSR1_REG             __REG(0x52000190)  //Out endpoint control status                 
#define     OUT_CSR2_REG             __REG(0x52000194)  //Out endpoint control status                 
#define     OUT_FIFO_CNT1_REG        __REG(0x52000198)  //Endpoint out write count                    
#define     OUT_FIFO_CNT2_REG        __REG(0x5200019C)  //Endpoint out write count                    
#define     EP0_FIFO                 __REG(0x520001C0)  //Endpoint 0 FIFO                             
#define     EP1_FIFO                 __REG(0x520001C4)  //Endpoint 1 FIFO                             
#define     EP2_FIFO                 __REG(0x520001C8)  //Endpoint 2 FIFO                             
#define     EP3_FIFO                 __REG(0x520001CC)  //Endpoint 3 FIFO                             
#define     EP4_FIFO                 __REG(0x520001D0)  //Endpoint 4 FIFO                             
#define     EP1_DMA_CON              __REG(0x52000200)  //EP1 DMA Interface control                   
#define     EP1_DMA_UNIT             __REG(0x52000204)  //EP1 DMA Tx unit counter                     
#define     EP1_DMA_FIFO             __REG(0x52000208)  //EP1 DMA Tx FIFO counter                     
#define     EP1_DMA_TTC_L            __REG(0x5200020C)  //EP1 DMA Total Tx counter                    
#define     EP1_DMA_TTC_M            __REG(0x52000210)  //EP1 DMA Total Tx counter                    
#define     EP1_DMA_TTC_H            __REG(0x52000214)  //EP1 DMA Total Tx counter                    
#define     EP2_DMA_CON              __REG(0x52000218)  //EP2 DMA interface control                   
#define     EP2_DMA_UNIT             __REG(0x5200021C)  //EP2 DMA Tx Unit counter                     
#define     EP2_DMA_FIFO             __REG(0x52000220)  //EP2 DMA Tx FIFO counter                     
#define     EP2_DMA_TTC_L            __REG(0x52000224)  //EP2 DMA total Tx counter                    
#define     EP2_DMA_TTC_M            __REG(0x52000228)  //EP2 DMA total Tx counter                    
#define     EP2_DMA_TTC_H            __REG(0x5200022C)  //EP2 DMA Total Tx counter                    
#define     EP3_DMA_CON              __REG(0x52000240)  //EP3 DMA Interface control                   
#define     EP3_DMA_UNIT             __REG(0x52000244)  //EP3 DMA Tx Unit counter                     
#define     EP3_DMA_FIFO             __REG(0x52000248)  //EP3 DMA Tx FIFO counter                     
#define     EP3_DMA_TTC_L            __REG(0x5200024C)  //EP3 DMA Total Tx counter                    
#define     EP3_DMA_TTC_M            __REG(0x52000250)  //EP3 DMA Total Tx counter                    
#define     EP3_DMA_TTC_H            __REG(0x52000254)  //EP3 DMA Total Tx counter                    
#define     EP4_DMA_CON              __REG(0x52000258)  //EP4 DMA Interface control                   
#define     EP4_DMA_UNIT             __REG(0x5200025C)  //EP4 DMA Tx Unit counter                     
#define     EP4_DMA_FIFO             __REG(0x52000260)  //EP4 DMA Tx FIFO counter                     
#define     EP4_DMA_TTC_L            __REG(0x52000264)  //EP4 DMA Total Tx counter                    
#define     EP4_DMA_TTC_M            __REG(0x52000268)  //EP4 DMA Total Tx counter                    
#define     EP4_DMA_TTC_H            __REG(0x5200026C)  //EP4 DMA Total Tx counter       
        
/* WOTCHDOG register */  
#define     WTCON                    __REG(0x53000000) 
#define     WTDAT                    __REG(0x53000004) 
#define     WTCNT                    __REG(0x53000008) 
        
/* I2C registers */ 
#define     IICCON  	             __REG(0x54000000)  // IIC control                    
#define     IICSTAT 	             __REG(0x54000004)  // IIC status                     
#define     IICADD  	             __REG(0x54000008)  // IIC address                    
#define     IICDS   	             __REG(0x5400000c)  // IIC data shift                 
#define     IICLC		             __REG(0x54000010)  //IIC multi-master line control   
                                                        
/*IIS*/                                                 
#define     IISCON 	                 __REG(0x55000000)  //HW,W R/W IIS control
#define     IISMOD 	                 __REG(0x55000004)  //IIS mode            
#define     IISPSR 	                 __REG(0x55000008)  //IIS prescaler       
#define     IISFCON	                 __REG(0x5500000C)  //IIS FIFO control    
#define     IISFIFO	                 __REG(0x55000010)  //HW IIS FIFO entry   
        
/*I/O port*/
#define     GPACON                   __REG(0x56000000)  //Port A control                           
#define     GPADAT                   __REG(0x56000004)  //Port A data                                      
#define     GPBCON                   __REG(0x56000010)  //Port B control                                   
#define     GPBDAT                   __REG(0x56000014)  //Port B data                                      
#define     GPBUP                    __REG(0x56000018)  //Pull-up control B                                
#define     GPCCON                   __REG(0x56000020)  //Port C control                                   
#define     GPCDAT                   __REG(0x56000024)  //Port C data                                      
#define     GPCUP                    __REG(0x56000028)  //Pull-up control C                                
#define     GPDCON                   __REG(0x56000030)  //Port D control                                   
#define     GPDDA1T                  __REG(0x56000034)  //Port D data                                      
#define     GPDUP                    __REG(0x56000038)  //Pull-up control D                                
#define     GPECON                   __REG(0x56000040)  //Port E control                                   
#define     GPEDAT                   __REG(0x56000044)  //Port E data                                      
#define     GPEUP                    __REG(0x56000048)  //Pull-up control E                                
#define     GPFCON                   __REG(0x56000050)  //Port F control                                   
#define     GPFDAT                   __REG(0x56000054)  //Port F data                                      
#define     GPFUP                    __REG(0x56000058)  //Pull-up control F                                
#define     GPGCON                   __REG(0x56000060)  //Port G control                                   
#define     GPGDAT                   __REG(0x56000064)  //Port G data                                      
#define     GPGUP                    __REG(0x56000068)  //Pull-up control G                                
#define     GPHCON                   __REG(0x56000070)  //Port H control                                   
#define     GPHDAT                   __REG(0x56000074)  //Port H data                                      
#define     GPHUP                    __REG(0x56000078)  //Pull-up control H                                
#define     GPJCON                   __REG(0x560000D0)  //Port J control                                   
#define     GPJDAT                   __REG(0x560000D4)  //Port J data                                      
#define     GPJUP                    __REG(0x560000D8)  //Pull-up control J                                
#define     MISCCR                   __REG(0x56000080)  //Miscellaneous control                            
#define     DCLKCON                  __REG(0x56000084)  //DCLK0/1 control                                  
#define     EXTINT0                  __REG(0x56000088)  //External interrupt control register 0            
#define     EXTINT1                  __REG(0x5600008C)  //External interrupt control register 1            
#define     EXTINT2                  __REG(0x56000090)  //External interrupt control register 2            
#define     EINTFLT0                 __REG(0x56000094)  //? W R/W Reserved                                 
#define     EINTFLT1                 __REG(0x56000098)  //Reserved                                         
#define     EINTFLT2                 __REG(0x5600009C)  //External interrupt filter control register 2     
#define     EINTFLT3                 __REG(0x560000A0)  //External interrupt filter control register 3     
#define     EINTMASK                 __REG(0x560000A4)  //External interrupt mask                          
#define     EINTPEND                 __REG(0x560000A8)  //External interrupt pending                       
#define     GSTATUS0                 __REG(0x560000AC)  //R External pin status                            
#define     GSTATUS1                 __REG(0x560000B0)  //R/W Chip ID                                      
#define     GSTATUS2                 __REG(0x560000B4)  //Reset status                                     
#define     GSTATUS3                 __REG(0x560000B8)  //Inform register                                  
#define     GSTATUS4                 __REG(0x560000BC)  //Inform register                                  
#define     MSLCON                   __REG(0x560000CC)  //Memory sleep control register                    
        
/*RTC*/     
#define     RTCCON 		             __REG(0x57000040)  //RTC control       
#define     TICNT  		             __REG(0x57000044)  //Tick time count   
#define     RTCALM 		             __REG(0x57000050)  //RTC alarm control 
#define     ALMSEC 		             __REG(0x57000054)  //Alarm second      
#define     ALMMIN 		             __REG(0x57000058)  //Alarm minute      
#define     ALMHOUR		             __REG(0x5700005C)  //Alarm hour        
#define     ALMDATE		             __REG(0x57000060)  //alarm day         
#define     ALMMON 		             __REG(0x57000064)  //Alarm month       
#define     ALMYEAR		             __REG(0x57000068)  //Alarm year        
#define     BCDSEC 		             __REG(0x57000070)  //BCD second        
#define     BCDMIN 		             __REG(0x57000074)  //BCD minute        
#define     BCDHOUR		             __REG(0x57000078)  //BCD hour          
#define     BCDDATE		             __REG(0x5700007C)  //BCD day           
#define     BCDDAY 		             __REG(0x57000080)  //BCD date          
#define     BCDMON 		             __REG(0x57000084)  //BCD month         
#define     BCDYEAR		             __REG(0x57000088)  //BCD year      
        
/*A/D Converte*/
#define     ADCCON                   __REG(0x58000000)  //ADC control                        
#define     ADCTSC                   __REG(0x58000004)  //ADC touch screen control           
#define     ADCDLY                   __REG(0x58000008)  //ADC start or interval delay        
#define     ADCDAT0                  __REG(0x5800000C)  //ADC conversion data                
#define     ADCDAT1                  __REG(0x58000010)  //ADC conversion data                
#define     ADCUPDN                  __REG(0x58000014)  //Stylus up or down interrupt status 

/*SPI CONTROL REGISTER*/ 
#define     SPCON0                   __REG(0x59000000)  //SPI channel 0 control register
#define     SPSTA0                   __REG(0x59000004)  //SPI channel 0 status register
#define     SPPIN0                   __REG(0x59000008)  //SPI channel 0 pin control register
#define     SPPRE0                   __REG(0x5900000C)  //SPI cannel 0 baud rate prescaler register
#define     SPTDAT0                  __REG(0x59000010)  //SPI channel 0 Tx data register
#define     SPRDAT0                  __REG(0x59000014)  //SPI channel 0 Rx data register
#define     SPCON1                   __REG(0x59000020)  //SPI channel 1 control register                                     
#define     SPSTA1                   __REG(0x59000024)  //SPI channel 1 status register                                     
#define     SPPIN1                   __REG(0x59000028)  // SPI channel 1 pin control register
#define     SPPRE1                   __REG(0x5900002C)  //SPI cannel 1 baud rate prescaler register
#define     SPTDAT1                  __REG(0x59000030)  //SPI channel 1 Tx data register                                    
#define     SPRDAT1                  __REG(0x59000034)  //SPI channel 1 Rx data register

/*SD Interface*/
#define     SDICON   		         __REG(0x5A000000)  //SDI control            
#define     SDIPRE   		         __REG(0x5A000004)  //SDI baud rate prescaler
#define     SDICARG  		         __REG(0x5A000008)  //SDI command argument   
#define     SDICCON  		         __REG(0x5A00000C)  //SDI command control    
#define     SDICSTA  		         __REG(0x5A000010)  //SDI command status     
#define     SDIRSP0  		         __REG(0x5A000014)  //SDI response           
#define     SDIRSP1  		         __REG(0x5A000018)  //SDI response           
#define     SDIRSP2  		         __REG(0x5A00001C)  //SDI response           
#define     SDIRSP3  		         __REG(0x5A000020)  //SDI response           
#define     SDIDTIMER		         __REG(0x5A000024)  //SDI data / busy timer  
#define     SDIBSIZE 		         __REG(0x5A000028)  //SDI block size         
#define     SDIDCON  		         __REG(0x5A00002C)  //SDI data control       
#define     SDIDCNT  		         __REG(0x5A000030)  //SDI data remain counter
#define     SDIDSTA  		         __REG(0x5A000034)  //SDI data status        
#define     SDIFSTA  		         __REG(0x5A000038)  //SDI FIFO status        
#define     SDIIMSK  		         __REG(0x5A00003C)  //SDI interrupt mask     
#define     SDIDAT   		         __REG(0x5A000040)  //SDI data               

#endif

4> uart.c

#include "s3c2440_soc.h"


/* 115200,8n1 */
void uart0_init()
{
	/* 设置引脚用于串口 */
	/* GPH2,3用于TxD0, RxD0 */
	GPHCON &= ~((3<<4) | (3<<6));
	GPHCON |= ((2<<4) | (2<<6));

	GPHUP &= ~((1<<2) | (1<<3));  /* 使能内部上拉 */
	

	/* 设置波特率 */
	/* UBRDIVn = (int)( UART clock / ( buad rate x 16) ) –1
	 *  UART clock = 50M
	 *  UBRDIVn = (int)( 50000000 / ( 115200 x 16) ) –1 = 26
	 */
	UCON0 = 0x00000005; /* PCLK,中断/查询模式 */
	UBRDIV0 = 26;

	/* 设置数据格式 */
	ULCON0 = 0x00000003; /* 8n1: 8个数据位, 无较验位, 1个停止位 */

	/*  */

}

int putchar(int c)
{
	/* UTRSTAT0 */
	/* UTXH0 */

	while (!(UTRSTAT0 & (1<<2)));
	UTXH0 = (unsigned char)c;
	
}

int getchar(void)
{
	while (!(UTRSTAT0 & (1<<0)));
	return URXH0;
}

int puts(const char *s)
{
	while (*s)
	{
		putchar(*s);
		s++;
	}
}

5> uart.h

#ifndef _UART_H
#define _UART_H

void uart0_init();
int putchar(int c);
int getchar(void);
int puts(const char *s);

#endif

6> Makefile

all:
	arm-linux-gcc -c -o led.o led.c
	arm-linux-gcc -c -o uart.o uart.c
	arm-linux-gcc -c -o main.o main.c
	arm-linux-gcc -c -o start.o start.S
	arm-linux-ld -Ttext 0 start.o led.o uart.o main.o -o uart.elf
	arm-linux-objcopy -O binary -S uart.elf uart.bin
	arm-linux-objdump -D uart.elf > uart.dis
clean:
	rm *.bin *.o *.elf *.dis

7> start.S


.text
.global _start

_start:

	/* 关闭看门狗 */
	ldr r0, =0x53000000
	ldr r1, =0
	str r1, [r0]

	/* 设置MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m */
	/* LOCKTIME(0x4C000000) = 0xFFFFFFFF */
	ldr r0, =0x4C000000
	ldr r1, =0xFFFFFFFF
	str r1, [r0]

	/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8  */
	ldr r0, =0x4C000014
	ldr r1, =0x5
	str r1, [r0]

	/* 设置CPU工作于异步模式 */
	mrc p15,0,r0,c1,c0,0
	orr r0,r0,#0xc0000000   //R1_nF:OR:R1_iA
	mcr p15,0,r0,c1,c0,0

	/* 设置MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0) 
	 *  m = MDIV+8 = 92+8=100
	 *  p = PDIV+2 = 1+2 = 3
	 *  s = SDIV = 1
	 *  FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M
	 */
	ldr r0, =0x4C000004
	ldr r1, =(92<<12)|(1<<4)|(1<<0)
	str r1, [r0]

	/* 一旦设置PLL, 就会锁定lock time直到PLL输出稳定
	 * 然后CPU工作于新的频率FCLK
	 */
	
	

	/* 设置内存: sp 栈 */
	/* 分辨是nor/nand启动
	 * 写0到0地址, 再读出来
	 * 如果得到0, 表示0地址上的内容被修改了, 它对应ram, 这就是nand启动
	 * 否则就是nor启动
	 */
	mov r1, #0
	ldr r0, [r1] /* 读出原来的值备份 */
	str r1, [r1] /* 0->[0] */ 
	ldr r2, [r1] /* r2=[0] */
	cmp r1, r2   /* r1==r2? 如果相等表示是NAND启动 */
	ldr sp, =0x40000000+4096 /* 先假设是nor启动 */
	moveq sp, #4096  /* nand启动 */
	streq r0, [r1]   /* 恢复原来的值 */
	

	bl main

halt:
	b halt

8> uart.dis

uart.elf:     file format elf32-littlearm

Disassembly of section .text:

00000000 <_start>:
   0:	e3a00453 	mov	r0, #1392508928	; 0x53000000
   4:	e3a01000 	mov	r1, #0	; 0x0
   8:	e5801000 	str	r1, [r0]
   c:	e3a00313 	mov	r0, #1275068416	; 0x4c000000
  10:	e3e01000 	mvn	r1, #0	; 0x0
  14:	e5801000 	str	r1, [r0]
  18:	e59f0044 	ldr	r0, [pc, #68]	; 64 <.text+0x64>
  1c:	e3a01005 	mov	r1, #5	; 0x5
  20:	e5801000 	str	r1, [r0]
  24:	ee110f10 	mrc	15, 0, r0, cr1, cr0, {0}
  28:	e3800103 	orr	r0, r0, #-1073741824	; 0xc0000000
  2c:	ee010f10 	mcr	15, 0, r0, cr1, cr0, {0}
  30:	e59f0030 	ldr	r0, [pc, #48]	; 68 <.text+0x68>
  34:	e59f1030 	ldr	r1, [pc, #48]	; 6c <.text+0x6c>
  38:	e5801000 	str	r1, [r0]
  3c:	e3a01000 	mov	r1, #0	; 0x0
  40:	e5910000 	ldr	r0, [r1]
  44:	e5811000 	str	r1, [r1]
  48:	e5912000 	ldr	r2, [r1]
  4c:	e1510002 	cmp	r1, r2
  50:	e59fd018 	ldr	sp, [pc, #24]	; 70 <.text+0x70>
  54:	03a0da01 	moveq	sp, #4096	; 0x1000
  58:	05810000 	streq	r0, [r1]
  5c:	eb00009f 	bl	2e0 <main>

00000060 <halt>:
  60:	eafffffe 	b	60 <halt>
  64:	4c000014 	stcmi	0, cr0, [r0], {20}
  68:	4c000004 	stcmi	0, cr0, [r0], {4}
  6c:	0005c011 	andeq	ip, r5, r1, lsl r0
  70:	40001000 	andmi	r1, r0, r0

00000074 <delay>:
  74:	e1a0c00d 	mov	ip, sp
  78:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
  7c:	e24cb004 	sub	fp, ip, #4	; 0x4
  80:	e24dd004 	sub	sp, sp, #4	; 0x4
  84:	e50b0010 	str	r0, [fp, #-16]
  88:	e51b3010 	ldr	r3, [fp, #-16]
  8c:	e2433001 	sub	r3, r3, #1	; 0x1
  90:	e50b3010 	str	r3, [fp, #-16]
  94:	e51b3010 	ldr	r3, [fp, #-16]
  98:	e3730001 	cmn	r3, #1	; 0x1
  9c:	0a000000 	beq	a4 <delay+0x30>
  a0:	eafffff8 	b	88 <delay+0x14>
  a4:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

000000a8 <led_test>:
  a8:	e1a0c00d 	mov	ip, sp
  ac:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
  b0:	e24cb004 	sub	fp, ip, #4	; 0x4
  b4:	e24dd008 	sub	sp, sp, #8	; 0x8
  b8:	e3a03000 	mov	r3, #0	; 0x0
  bc:	e50b3010 	str	r3, [fp, #-16]
  c0:	e3a02456 	mov	r2, #1442840576	; 0x56000000
  c4:	e2822050 	add	r2, r2, #80	; 0x50
  c8:	e3a03456 	mov	r3, #1442840576	; 0x56000000
  cc:	e2833050 	add	r3, r3, #80	; 0x50
  d0:	e5933000 	ldr	r3, [r3]
  d4:	e3c33c3f 	bic	r3, r3, #16128	; 0x3f00
  d8:	e5823000 	str	r3, [r2]
  dc:	e3a02456 	mov	r2, #1442840576	; 0x56000000
  e0:	e2822050 	add	r2, r2, #80	; 0x50
  e4:	e3a03456 	mov	r3, #1442840576	; 0x56000000
  e8:	e2833050 	add	r3, r3, #80	; 0x50
  ec:	e5933000 	ldr	r3, [r3]
  f0:	e3833c15 	orr	r3, r3, #5376	; 0x1500
  f4:	e5823000 	str	r3, [r2]
  f8:	e51b3010 	ldr	r3, [fp, #-16]
  fc:	e1e03003 	mvn	r3, r3
 100:	e50b3014 	str	r3, [fp, #-20]
 104:	e51b3014 	ldr	r3, [fp, #-20]
 108:	e2033007 	and	r3, r3, #7	; 0x7
 10c:	e50b3014 	str	r3, [fp, #-20]
 110:	e3a02456 	mov	r2, #1442840576	; 0x56000000
 114:	e2822054 	add	r2, r2, #84	; 0x54
 118:	e3a03456 	mov	r3, #1442840576	; 0x56000000
 11c:	e2833054 	add	r3, r3, #84	; 0x54
 120:	e5933000 	ldr	r3, [r3]
 124:	e3c33070 	bic	r3, r3, #112	; 0x70
 128:	e5823000 	str	r3, [r2]
 12c:	e3a01456 	mov	r1, #1442840576	; 0x56000000
 130:	e2811054 	add	r1, r1, #84	; 0x54
 134:	e3a03456 	mov	r3, #1442840576	; 0x56000000
 138:	e2833054 	add	r3, r3, #84	; 0x54
 13c:	e51b2014 	ldr	r2, [fp, #-20]
 140:	e1a02202 	mov	r2, r2, lsl #4
 144:	e5933000 	ldr	r3, [r3]
 148:	e1833002 	orr	r3, r3, r2
 14c:	e5813000 	str	r3, [r1]
 150:	e3a00b61 	mov	r0, #99328	; 0x18400
 154:	e2800e2a 	add	r0, r0, #672	; 0x2a0
 158:	ebffffc5 	bl	74 <delay>
 15c:	e51b3010 	ldr	r3, [fp, #-16]
 160:	e2833001 	add	r3, r3, #1	; 0x1
 164:	e50b3010 	str	r3, [fp, #-16]
 168:	e51b3010 	ldr	r3, [fp, #-16]
 16c:	e3530008 	cmp	r3, #8	; 0x8
 170:	1affffe0 	bne	f8 <led_test+0x50>
 174:	e3a03000 	mov	r3, #0	; 0x0
 178:	e50b3010 	str	r3, [fp, #-16]
 17c:	eaffffdd 	b	f8 <led_test+0x50>

00000180 <uart0_init>:
 180:	e1a0c00d 	mov	ip, sp
 184:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
 188:	e24cb004 	sub	fp, ip, #4	; 0x4
 18c:	e3a02456 	mov	r2, #1442840576	; 0x56000000
 190:	e2822070 	add	r2, r2, #112	; 0x70
 194:	e3a03456 	mov	r3, #1442840576	; 0x56000000
 198:	e2833070 	add	r3, r3, #112	; 0x70
 19c:	e5933000 	ldr	r3, [r3]
 1a0:	e3c330f0 	bic	r3, r3, #240	; 0xf0
 1a4:	e5823000 	str	r3, [r2]
 1a8:	e3a02456 	mov	r2, #1442840576	; 0x56000000
 1ac:	e2822070 	add	r2, r2, #112	; 0x70
 1b0:	e3a03456 	mov	r3, #1442840576	; 0x56000000
 1b4:	e2833070 	add	r3, r3, #112	; 0x70
 1b8:	e5933000 	ldr	r3, [r3]
 1bc:	e38330a0 	orr	r3, r3, #160	; 0xa0
 1c0:	e5823000 	str	r3, [r2]
 1c4:	e3a02456 	mov	r2, #1442840576	; 0x56000000
 1c8:	e2822078 	add	r2, r2, #120	; 0x78
 1cc:	e3a03456 	mov	r3, #1442840576	; 0x56000000
 1d0:	e2833078 	add	r3, r3, #120	; 0x78
 1d4:	e5933000 	ldr	r3, [r3]
 1d8:	e3c3300c 	bic	r3, r3, #12	; 0xc
 1dc:	e5823000 	str	r3, [r2]
 1e0:	e3a02245 	mov	r2, #1342177284	; 0x50000004
 1e4:	e3a03005 	mov	r3, #5	; 0x5
 1e8:	e5823000 	str	r3, [r2]
 1ec:	e3a03205 	mov	r3, #1342177280	; 0x50000000
 1f0:	e2833028 	add	r3, r3, #40	; 0x28
 1f4:	e3a0201a 	mov	r2, #26	; 0x1a
 1f8:	e5832000 	str	r2, [r3]
 1fc:	e3a02205 	mov	r2, #1342177280	; 0x50000000
 200:	e3a03003 	mov	r3, #3	; 0x3
 204:	e5823000 	str	r3, [r2]
 208:	e89da800 	ldmia	sp, {fp, sp, pc}

0000020c <putchar>:
 20c:	e1a0c00d 	mov	ip, sp
 210:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
 214:	e24cb004 	sub	fp, ip, #4	; 0x4
 218:	e24dd004 	sub	sp, sp, #4	; 0x4
 21c:	e50b0010 	str	r0, [fp, #-16]
 220:	e3a03205 	mov	r3, #1342177280	; 0x50000000
 224:	e2833010 	add	r3, r3, #16	; 0x10
 228:	e5933000 	ldr	r3, [r3]
 22c:	e2033004 	and	r3, r3, #4	; 0x4
 230:	e3530000 	cmp	r3, #0	; 0x0
 234:	1a000000 	bne	23c <putchar+0x30>
 238:	eafffff8 	b	220 <putchar+0x14>
 23c:	e3a03205 	mov	r3, #1342177280	; 0x50000000
 240:	e2833020 	add	r3, r3, #32	; 0x20
 244:	e51b2010 	ldr	r2, [fp, #-16]
 248:	e5c32000 	strb	r2, [r3]
 24c:	e1a00003 	mov	r0, r3
 250:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

00000254 <getchar>:
 254:	e1a0c00d 	mov	ip, sp
 258:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
 25c:	e24cb004 	sub	fp, ip, #4	; 0x4
 260:	e3a03205 	mov	r3, #1342177280	; 0x50000000
 264:	e2833010 	add	r3, r3, #16	; 0x10
 268:	e5933000 	ldr	r3, [r3]
 26c:	e2033001 	and	r3, r3, #1	; 0x1
 270:	e3530000 	cmp	r3, #0	; 0x0
 274:	1a000000 	bne	27c <getchar+0x28>
 278:	eafffff8 	b	260 <getchar+0xc>
 27c:	e3a03205 	mov	r3, #1342177280	; 0x50000000
 280:	e2833024 	add	r3, r3, #36	; 0x24
 284:	e5d33000 	ldrb	r3, [r3]
 288:	e20330ff 	and	r3, r3, #255	; 0xff
 28c:	e1a00003 	mov	r0, r3
 290:	e89da800 	ldmia	sp, {fp, sp, pc}

00000294 <puts>:
 294:	e1a0c00d 	mov	ip, sp
 298:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
 29c:	e24cb004 	sub	fp, ip, #4	; 0x4
 2a0:	e24dd004 	sub	sp, sp, #4	; 0x4
 2a4:	e50b0010 	str	r0, [fp, #-16]
 2a8:	e51b3010 	ldr	r3, [fp, #-16]
 2ac:	e5d33000 	ldrb	r3, [r3]
 2b0:	e3530000 	cmp	r3, #0	; 0x0
 2b4:	0a000007 	beq	2d8 <puts+0x44>
 2b8:	e51b3010 	ldr	r3, [fp, #-16]
 2bc:	e5d33000 	ldrb	r3, [r3]
 2c0:	e1a00003 	mov	r0, r3
 2c4:	ebffffd0 	bl	20c <putchar>
 2c8:	e51b3010 	ldr	r3, [fp, #-16]
 2cc:	e2833001 	add	r3, r3, #1	; 0x1
 2d0:	e50b3010 	str	r3, [fp, #-16]
 2d4:	eafffff3 	b	2a8 <puts+0x14>
 2d8:	e1a00003 	mov	r0, r3
 2dc:	e89da808 	ldmia	sp, {r3, fp, sp, pc}

000002e0 <main>:
 2e0:	e1a0c00d 	mov	ip, sp
 2e4:	e92dd800 	stmdb	sp!, {fp, ip, lr, pc}
 2e8:	e24cb004 	sub	fp, ip, #4	; 0x4
 2ec:	e24dd004 	sub	sp, sp, #4	; 0x4
 2f0:	ebffffa2 	bl	180 <uart0_init>
 2f4:	e59f0044 	ldr	r0, [pc, #68]	; 340 <.text+0x340>
 2f8:	ebffffe5 	bl	294 <puts>
 2fc:	ebffffd4 	bl	254 <getchar>
 300:	e1a03000 	mov	r3, r0
 304:	e54b300d 	strb	r3, [fp, #-13]
 308:	e55b300d 	ldrb	r3, [fp, #-13]
 30c:	e353000d 	cmp	r3, #13	; 0xd
 310:	1a000001 	bne	31c <main+0x3c>
 314:	e3a0000a 	mov	r0, #10	; 0xa
 318:	ebffffbb 	bl	20c <putchar>
 31c:	e55b300d 	ldrb	r3, [fp, #-13]
 320:	e353000a 	cmp	r3, #10	; 0xa
 324:	1a000001 	bne	330 <main+0x50>
 328:	e3a0000d 	mov	r0, #13	; 0xd
 32c:	ebffffb6 	bl	20c <putchar>
 330:	e55b300d 	ldrb	r3, [fp, #-13]
 334:	e1a00003 	mov	r0, r3
 338:	ebffffb3 	bl	20c <putchar>
 33c:	eaffffee 	b	2fc <main+0x1c>
 340:	00000344 	andeq	r0, r0, r4, asr #6
Disassembly of section .rodata:

00000344 <.rodata>:
 344:	6c6c6548 	cfstr64vs	mvdx6, [ip], #-288
 348:	77202c6f 	strvc	r2, [r0, -pc, ror #24]!
 34c:	646c726f 	strvsbt	r7, [ip], #-623
 350:	000d0a21 	andeq	r0, sp, r1, lsr #20
Disassembly of section .comment:

00000000 <.comment>:
   0:	43434700 	cmpmi	r3, #0	; 0x0
   4:	4728203a 	undefined
   8:	2029554e 	eorcs	r5, r9, lr, asr #10
   c:	2e342e33 	mrccs	14, 1, r2, cr4, cr3, {1}
  10:	47000035 	smladxmi	r0, r5, r0, r0
  14:	203a4343 	eorcss	r4, sl, r3, asr #6
  18:	554e4728 	strplb	r4, [lr, #-1832]
  1c:	2e332029 	cdpcs	0, 3, cr2, cr3, cr9, {1}
  20:	00352e34 	eoreqs	r2, r5, r4, lsr lr
  24:	43434700 	cmpmi	r3, #0	; 0x0
  28:	4728203a 	undefined
  2c:	2029554e 	eorcs	r5, r9, lr, asr #10
  30:	2e342e33 	mrccs	14, 1, r2, cr4, cr3, {1}
  34:	Address 0x34 is out of bounds.

9> uart.bin

5304 a0e3 0010 a0e3 0010 80e5 1303 a0e3
0010 e0e3 0010 80e5 4400 9fe5 0510 a0e3
0010 80e5 100f 11ee 0301 80e3 100f 01ee
3000 9fe5 3010 9fe5 0010 80e5 0010 a0e3
0000 91e5 0010 81e5 0020 91e5 0200 51e1
18d0 9fe5 01da a003 0000 8105 9f00 00eb
feff ffea 1400 004c 0400 004c 11c0 0500
0010 0040 0dc0 a0e1 00d8 2de9 04b0 4ce2
04d0 4de2 1000 0be5 1030 1be5 0130 43e2
1030 0be5 1030 1be5 0100 73e3 0000 000a
f8ff ffea 08a8 9de8 0dc0 a0e1 00d8 2de9
04b0 4ce2 08d0 4de2 0030 a0e3 1030 0be5
5624 a0e3 5020 82e2 5634 a0e3 5030 83e2
0030 93e5 3f3c c3e3 0030 82e5 5624 a0e3
5020 82e2 5634 a0e3 5030 83e2 0030 93e5
153c 83e3 0030 82e5 1030 1be5 0330 e0e1
1430 0be5 1430 1be5 0730 03e2 1430 0be5
5624 a0e3 5420 82e2 5634 a0e3 5430 83e2
0030 93e5 7030 c3e3 0030 82e5 5614 a0e3
5410 81e2 5634 a0e3 5430 83e2 1420 1be5
0222 a0e1 0030 93e5 0230 83e1 0030 81e5
610b a0e3 2a0e 80e2 c5ff ffeb 1030 1be5
0130 83e2 1030 0be5 1030 1be5 0800 53e3
e0ff ff1a 0030 a0e3 1030 0be5 ddff ffea
0dc0 a0e1 00d8 2de9 04b0 4ce2 5624 a0e3
7020 82e2 5634 a0e3 7030 83e2 0030 93e5
f030 c3e3 0030 82e5 5624 a0e3 7020 82e2
5634 a0e3 7030 83e2 0030 93e5 a030 83e3
0030 82e5 5624 a0e3 7820 82e2 5634 a0e3
7830 83e2 0030 93e5 0c30 c3e3 0030 82e5
4522 a0e3 0530 a0e3 0030 82e5 0532 a0e3
2830 83e2 1a20 a0e3 0020 83e5 0522 a0e3
0330 a0e3 0030 82e5 00a8 9de8 0dc0 a0e1
00d8 2de9 04b0 4ce2 04d0 4de2 1000 0be5
0532 a0e3 1030 83e2 0030 93e5 0430 03e2
0000 53e3 0000 001a f8ff ffea 0532 a0e3
2030 83e2 1020 1be5 0020 c3e5 0300 a0e1
08a8 9de8 0dc0 a0e1 00d8 2de9 04b0 4ce2
0532 a0e3 1030 83e2 0030 93e5 0130 03e2
0000 53e3 0000 001a f8ff ffea 0532 a0e3
2430 83e2 0030 d3e5 ff30 03e2 0300 a0e1
00a8 9de8 0dc0 a0e1 00d8 2de9 04b0 4ce2
04d0 4de2 1000 0be5 1030 1be5 0030 d3e5
0000 53e3 0700 000a 1030 1be5 0030 d3e5
0300 a0e1 d0ff ffeb 1030 1be5 0130 83e2
1030 0be5 f3ff ffea 0300 a0e1 08a8 9de8
0dc0 a0e1 00d8 2de9 04b0 4ce2 04d0 4de2
a2ff ffeb 4400 9fe5 e5ff ffeb d4ff ffeb
0030 a0e1 0d30 4be5 0d30 5be5 0d00 53e3
0100 001a 0a00 a0e3 bbff ffeb 0d30 5be5
0a00 53e3 0100 001a 0d00 a0e3 b6ff ffeb
0d30 5be5 0300 a0e1 b3ff ffeb eeff ffea
4403 0000 4865 6c6c 6f2c 2077 6f72 6c64
210a 0d00

 

-西西弗斯
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