SDIO 支持

7项IO功能、一项存储功能

超时标准-1s

ACMD41-CMD5  R4 ans

CSA 代码存储区域

Re-initialize Both I/O and Memory
When the host re-initializes both the I/O and Memory controllers, it is strongly recommended that the host either execute a power reset (power off then on) or issues reset commands to both controllers prior to any other  operation.  If  the  host chooses  to  use  the  reset  commands,  it shall  issue  CMD52  (I/O  Reset)  first, because it cannot issue CMD52 after CMD0 (Refer to Section 4.4). After the reset, the host shall re-initialize both the I/O and Memory controller as defined in Figure 3-2.

Acceptable Commands after Initialization

Note that CMD15 (GO_INACTIVE_STATE) can be sent at any time after initialization in order to put any addressed memory controller into the inactive state.

Recommendations for RCA after Reset

The host shall not issue any commands to the Combo Card except for CMD0, CMD5, CMD3 or CMD7 until the I/O controller has transitioned to the cmd state.

An important fact for the host designer to note is that the host shall not issue any commands except for CMD0, ACMD41 (with RCA=0000h), CMD2, CMD3 or CMD7 to the Combo Card until the memory controller has transitioned to the tran state.

Enabling CRC in SPI Combo Card

When receiving CMD59, Combo cards shall synchronize CRC enable in both SDIO and memory portions of the  card.   If  a  host  enables  CRC  using  CMD59  and  subsequently  re-initializes  either  the  I/O  or  memory controller, the CRC for that controller will be off by default and the host shall issue a CMD59 to re-enable CRC.  When CMD59 is received, Combo Cards return the R1 response token while SDIO only cards return the modified R1 response token.

 

Modified R6 Response

Reset for SDIO

The  reset  command  (CMD0)  is  only  used  for  memory  or  the memory portion of Combo cards. In order to reset an I/O only card or the I/O portion of a combo card, use CMD52 to write a 1 to the RES bit in the CCCR (bit 3 of register 6). Note that in the SD mode, CMD0 is only used to indicate entry into SPI mode and shall be supported. An I/O only card or the I/O portion of a combo card is not reset by CMD0.

Bus Width

or an SD memory card, the bus width for SD mode is set using ACMD6. For an SDIO card a write to the CCCR using CMD52 is used to select bus width. In the case of a combo card, both selection methods exist. In this case, the host shall set the bus width in both locations by issuing both the ACMD6 and the CCCR write using CMD52 with the same width before starting any data transfers. For details on changing the bus for an SDIO card, refer to Table 6-2. For a Combo Card, changing bus width is handled as shown in Table 4-5.

Note  that  Low-Speed  SDIO  cards  support  4-bit  transfer  as  an  option.  When  communicating  with  a Low-Speed SDIO card, the host shall first determine if the card supports 4-bit transfer prior to attempting to select that mode.

If a Combo card supports the lock/unlock operation, it cannot change bus width of a locked card and returns an illegal command error to a bus width switch command.  The host needs to unlock the card by CMD42 before changing bus width.  This also implies that the host should not change bus width during initialization before managing a locked card.

Only 4-bit bus mode is supported in UHS-I except CMD42 (As unlocking is required before changing 4-bit mode, CMD42 sends a data block in 1-bit mode). UHS-I operating in 1-bit mode is not assured.

Card Detect Resistor

SD  memory  and  I/O  cards  use  a  pull-up  resistor  on  DAT[3]  to  detect  card  insertion.  The  procedure  to enable/disable this resistor is different between SD memory and SDIO. SD memory uses ACMD42 to control this resistor while SDIO uses writes to the CCCR using CMD52. In the case of a combo card, both control locations exist and shall be managed by the host. For a combo card, the resistor is enabled only when both the memory and the I/O control registers have the resistor enabled. That is, after a power on, the host shall disable the resistor by sending ACMD42 to the memory controller or a CCCR write to the SDIO controller since the resistor enable is a logical AND of the two enables. Table 4-6 shows the effect of each resistor enable on the card's resistor. After power-up, both locations default to resistor enabled. Note that after an I/O reset, the I/O resistor enable is not changed. Also note that SDIO Specification Version 1.00 required that both the SDIO and Memory resistor be disabled in order for the resistor to actually be disabled (logical OR of he  2  enables).  Combo  cards  built  to that  specification  require  the  host  to  disable  both  enables.  It  is recommended  the  host  disable  both  enables  of  any  combo  card  to  avoid  problems  with  the  difference between 1.0 and current specification based cards.

Data Transfer Block Sizes

SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format, while the SD memory cards are fixed in the block transfer mode. The Physical Layer Specification limits the block size for data  transfer  to  powers  of  2  (i.e.  512,  1024,  2048) unless  using  partial  read  and  write.  The  SDIO Specification allows any block size from 1 byte to 2048 bytes in order to accommodate the various natural block sizes for I/O functions. Note that an SDIO card function may define a maximum block size or byte count in the CIS that is smaller than the maximum values described above.

Data Transfer Abort

A host communicating with a SD memory card uses CMD12 to abort the transfer of read or write data to/from the card. For an SDIO card, CMD12 abort is replaced by a write to the ASx bits in the CCCR. Normally, the abort  is  used  to  stop  an  infinite  block  transfer  (block  count=0).  If  an  exact  number  of  blocks  are  to  be transferred, it is recommended that the host issue a block command with the correct block count, rather than using an infinite count and aborting the data at the correct time.

Read Abort

The host may issue an I/O abort by writing to the CCCR at any time during I/O extended read operation. The data transmission stops 2 clocks cycles after the end bit of the I/O abort command, even if the card has already begun transferring an unwanted data block while the host is issuing the abort.

Write Abort

The host may issue an I/O abort by writing to the CCCR at any time between data blocks during I/O extended write operation. In this case, the final block transfer (including the CRC response from the card) shall be completed. This requires that the end bit of the I/O abort command appear a maximum of two clocks before the end bit of the CRC response to the last data block. Note that the I/O abort command may be sent any time after the CRC response to the last data block. The host shall not abort in the middle of a write block. After the I/O abort is sent to the card, the card signals 'Busy' (by pulling DAT[0] line to '0') until it has finished processing the last transferred data block. During that Busy period, the host may release the bus by writing to the CCCR BR bit. There exist some special cases when the abort is issued near the end of the CRC response to a write multiple-block command.

Changes to SD Memory Fixed Registers

The Physical Layer Specification defines 7 fixed card registers. They are:
1. OCR Register (32 bits)
2.  CID Register (128 bits)
3. CSD Register (128 bits)
4.  RCA Register (16 bits)
5. DSR Register (16 bits, optional)
6. SCR Register (64 bits)
7. SD_CARD_STATUS (512 bits)

In addition, within an SD memory card there is a status register whose value is returned to the host in the form  of  several  responses  (i.e.  the  R1b  response). An  SDIO  only  card  eliminates  some  registers  and changes some of the bits in the remaining registers. 

OCR Register

All SD cards (memory, I/O and combo) shall have at least one OCR register. If the card is a combo card, it
may have two OCR's (one for memory and one for I/O). The memory portion of a combo card has an OCR accessed using ACMD41 and CMD58. The I/O portion of a card has an OCR with the same structure that is accessed via CMD5. If there are multiple OCR's the voltage range may not be identical. Some I/O functions may have a wider VDD range than that reflected in the I/O OCR register. The I/O OCR shall be the logical AND of the voltage ranges(s) of all I/O functions. Note that the I/O OCR format is different from the memory version in that it is only 24 bits long. 

CID Register

There shall be a maximum of one CID register per SD card. If the card contains both memory and I/O, the CID register information is unchanged from the Physical Layer Specification Version 1.01 and reflects the information from the memory portion of the card. If the card is I/O only, the CID register and the associated access command (CMD10) are not supported. If the host attempts to access this register in an I/O only card, a card in SPI mode shall respond with an "Invalid Command" error response and a card in SD mode shall not respond.

CSD Register

There shall be a maximum of one CSD register per SD card. If the card contains both memory and I/O, the CSD register information is unchanged from the Physical Layer Specification Version 1.01 and reflects the information from the memory portion of the card. If the card is I/O only, the CSD register and the associated access command (CMD9) are not supported. If the host attempts to access this register in an I/O only card, a card in SPI mode shall respond with an "Invalid Command" error response and a card in SD mode shall not respond.

RCA Register

There shall only be one RCA register per SD card. The RCA value shall apply to the card as a whole. All functions and any memory share the same card address.

DSR Register

SDIO only cards do not support the DSR register. In the case of combo cards, support is optional as defined in the Physical Layer Specification.

SCR Register

here shall be a maximum of one SCR register per SD card. If the card contains both memory and I/O, the SCR register information is unchanged from the Physical Layer Specification Version 1.01 and reflects the information from the memory portion of the card. If the card is I/O only, the SCR register and the associated access command (ACMD51) are not supported. If the host attempts to access this register in an I/O only card, a card in SPI mode shall respond with an "Invalid Command" error response and a card in SD mode shall not respond.

SD Status

There shall be a maximum of one SD Status register per SD card. If the card contains both memory and I/O, the  SD  Status  register  information  is  unchanged  from  the  Physical  Layer  Specification  Version  1.01  and reflects the information from the memory portion of the card. If the card is I/O only, the SD Status register and the associated access command (ACMD13) are not supported. If the host attempts to access this register in an I/O only card, a card in SPI mode shall respond with an "Invalid Command" error response and a card in SD mode shall not respond.

Card Status Register

Note 1: In the SPI mode, if the card detects a CRC error, it returns a com CRC error in the R1 response immediately following the command (Refer to Figure 3-7). In this situation, the note that the CRC error is for the previous command does not apply.
Note 2: In the SPI mode, if the card detects an Illegal Command, it returns an Illegal Command error in the R1 response immediately following the command (Refer to Figure 3-7). In this situation, the note that the Illegal Command error is for the previous command does not apply.

New I/O Read/Write Commands

Two  additional  data  transfer  instructions have  been  added  to  support  I/O.  IO_RW_DIRECT  and IO_RW_EXTENDED, which allows fast access with byte or block addresses. Both commands are in class 9
(I/O Commands).

New I/O Read/Write Commands

Two  additional  data  transfer  instructions have  been  added  to  support  I/O.  IO_RW_DIRECT  and IO_RW_EXTENDED, which allows fast access with byte or block addresses. Both commands are in class 9(I/O Commands).

The  IO_RW_DIRECT  is  the  simplest  means  to  access a  single  register  within  the  total  128K  of  register space in any I/O function, including the common I/O area (CIA). This command reads or writes 1 byte using only  1  command/response  pair.  A  common  use  is  to  initialize  registers  or  monitor  status  values  for  I/O functions. This command is the fastest means to read or write single I/O registers, as it requires only a single command/response pair.

 IO_RW_DIRECT Response (R5)

The SDIO card's response to CMD52 shall be in one of two formats. If the communication between the card and host is in the 1-bit or 4-bit SD mode, the response shall be in a 48-bit response (R5) as described in Section 5.2.1. If the communication is using the SPI mode, the response shall be a 16-bit R5 response as described in Section 5.2.2.

CMD52 Response (SD Modes)

The SDIO card's response to CMD52 in the SD mode is shown in Figure 5-2. If the operation was a read command,  the  data  being  read  is  returned  as  an  8-bit  value.  In  addition,  15  bits  of status  information  is returned. The format of the SD response is as follows:

Read or Write Data:  For an I/O write (R/W=1) with the RAW Flag set (RAW=1) this field shall contain the value read from the addressed register after the write of the data contained in the command. Note that in this case, the read-back data may not be the same as the data written to the register, depending on the design of the hardware. For an I/O write with the RAW bit=0, the SDIO function shall not do a read after write operation, and the data in this field shall be identical to the data byte in the write command. For an I/O read (R/W=0), the actual value read from that I/O location is returned in this field. 

 IO_RW_EXTENDED Command (CMD53)

In  order  to  read  and  write  multiple  I/O  registers  with  a  single  command,  a  new  command, IO_RW_EXTENDED  is  defined.  This  command  is  included  in  command  class  9  (I/O  Commands).  This command allows the reading or writing of a large number of I/O registers with a single command. Since this is a data transfer command, it provides the highest possible transfer rate.

R/W Flag:  This  bit  determines  the direction  of  the  I/O  operation. If  this  bit  is  0,  this  command
reads data from the SDIO card at the address specified by the Function Number and the Register Address to the host. The read data shall be returned on the DAT[x] lines. If this bit is set to 1, the command shall write the bytes from the DAT[x] lines to the I/O location addressed by the Function Number and the Register Address.

Block Mode  (Optional)  this  bit,  if  set  to  1,  indicates  that  the  read  or  write  operation  shall  be
performed  on  a  block  basis,  rather  than  the  normal  byte  basis.  If  this  bit  is  set,  the Byte/Block  count  value  shall  contain  the number  of  blocks  to be  read/written.  The block size for functions 1-7 is set by writing the block size to the I/O block size register in the FBR (Refer to Table 6-3 and Table 6-4). The block size for function 0 is set by writing to the FN0 Block Size register in the CCCR. Card and host support of the block I/O mode is optional. The host can determine if a card supports block I/O by reading the Card supports MBIO bit (SMB) in the CCCR (Refer to Table 6-2). The block size used when Block Mode = 1 and the maximum byte count per command used when Block Mode = 0 can be read from the CIS in the tuple TPLFE_MAX_BLK_SIZE (Refer to Section 16.7.4) on a per-function basis.

OP Code 0 is used to read or write multiple bytes of data to/from a single I/O register address. This command is useful when I/O data is transferred using a FIFO inside of the I/O card. In this case, multiple bytes of data are transferred to/from a single register address. For this operation, the address of the register is set into the Register Address field. Data is transferred on the DAT[0] or DAT[3:0] lines as defined for SD memory cards.
OP  Code  1  is  used  to  read  or  write  multiple  bytes  of  data  to/from  an  I/O  register address that increment by 1 after each operation. This command is used when large amounts of I/O data exist within the I/O card in a RAM like data buffer. In this operation, the start address is loaded into the Register Address field. The first operation occurs at that address within the I/O card. The next operation shall occur at address+1 with the address incrementing by 1 until the operation has completed. As with OP Code 0, the number of bytes is set in the Byte Count field of the command.