宏模块的简单使用

简单计数移向模块

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;   --invold '+'  '-'
use ieee.std_logic_arith.all;      --  invold * mul   unsigned

ENTITY   phase3   IS
 PORT(  wave1,wave2,clk  :IN STD_LOGIC;
            en:out STD_LOGIC;            
            choose:out std_logic_vector(1 downto 0);  
            phase:out std_logic_vector(15 downto 0)
                                                          );
END phase3 ;

ARCHITECTURE   behv  OF   phase3     IS

SIGNAL c0   : std_logic;
SIGNAL locked   : std_logic;

SIGNAL  denom  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  numer  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  quotient :  STD_LOGIC_VECTOR (29 DOWNTO 0);

SIGNAL  quo      :  STD_LOGIC_VECTOR (29 DOWNTO 0);  

SIGNAL  dataa  :  STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL  result  :  STD_LOGIC_VECTOR (41 DOWNTO 0);