嵌入式操作系统 《ARM System Developer's Guide》

本章包含两部分:
1. 讲述组成嵌入式操作系统的基础组件和关于ARM处理器的特殊问题
2. 通过简单的嵌入式操作系统Simple Little Operating System(SLOS) 来看看基础组件的实现

Fundamental Components

Componentsfunction
Initialization在firmware移交控制权后第一段执行的代码。用于设立内部数据结构,全局变量,硬件,初始化设备驱动,设立可变控制寄存器。
Memory handling设计建立系统和任务栈。system stack定位在哪里是第一阶段决定的。而task stack则依赖于其是静态的还是动态的。详细内容p382
handling interrupts and exceptions基本上所有操作系统设计的时候都需要处理异常和中断。而不是所有的异常都需要handler的,这时候可以将infinite loop作为unused exceptions.这样做便于DEBUG和保护系统。
periodic interruptfor a preemptive operating system。由目标硬件的定时器或者计数器产生。
pollingfor a nonpreemptive operating system。持续检查目标设备状态的改变。对于特定的状态改变产生相应的处理。
scheduler决定接下来哪个任务被执行的算法。最简单之一的算法是round-robin algorithm。scheduler algorithm将会在性能和算法复杂度上取得平衡。当任务完成时,新旧任务的切换通过context switch完成。context switch将所有的旧任务寄存器的值从processor保存到数据结构中去。而新任务寄存器的值加载到processor中。
device driver framework操作系统上的一种机制,在不同硬件外设之间提供了恒定的接口。便于操作系统支持新的外设。framework也提供了安全的方法访问外设(比如拒绝多个应用同时访问一个外设)

Example:Simple Little Operating System

以上就是7种嵌入式操作系统的基础组件。本部分通过实例SLOS来展现基础组件的具体实现。

Initialization

There are three main stages pf initialization SLOS.(具体内容见p385)
1. startup-sets up FIQ registers and SVC,System,IRQ mode stacks.
2. PCB stepup code-initialize PCB,which contains task’s states and all registers
3. C initialization code-initialize device driver, event handler and periodic timer

Memory Model

(具体图片见p390)

We adpoted a simple memory model for SLOS.Code portion are located in low momery.The stacks for IRQ and for each task are loacted in high memory.SVC stack is located in top of memory.The arrows in the memeory show the dirction of stack growth.

Interrupts and Exceptions Handling

我们仅仅使用了3种异常,其余异常handler均设置为dummy handlers。

ExceptionPurpose
ResetInitialize the OS
SWImechanism to access the device drivers
IRQmechanism to service events

Reset

理论上可以用其重新初始化系统,例如在响应watchdog的时候对系统进行重启。

SWI

SWI指令强制processor从user模式进入SVC模式。在SWI handler中保存相应寄存器值并且跳转到C handler进行相应处理,r0包含SWI number,r1指向 存储在SVC stack中的寄存器。
(代码见p392)

IRQ

IRQ handler比SWI handler简单很多。是一种基础的无嵌套中断handler。The handler first saves the context and then copied the contents of the interrupt contrller status register,INTPND,int register r0.If r0 is matched with a particular interrupt source, then the service routine is called.

最简单的例子:

eventsTickVener
    BL eventsTickService; //reset tick hardware
    B  kernelScheduler;   //branch to scheduler

解释:当发生定时器中断时,重置定时器的值,并且执行了一次内核调度。

Scheduler

The low-level shceduler, or dispatcher, used in SLOS is a simple round-robin algorithm.following:

//pseudocode
task t = 0;
task t';

scheduler()
{
    t' = t + 1;
    if(t' == MAX_NUMBER_OF)TASKS)
    {
        t' = 0;
    }
    ContextSwitch(t, t');
}

执行Scheduler的结果如下:
1. PCB_PtrCurrentTask指向当前激活的PCB的地址
2. PCB_PtrNextTask指向下个激活的PCB的地址
3. PCB_CurrentTask holds the value of the next task identifier

Context Switch

通过使用scheduler更新后的信息,context switch完成task t和task t’之间的切换。为完成切换,需要经过two stage:(图解见p396)

stage-1 Save the Current Context

作用:
1. reset the IRQ stack and save it to PCB_IRQStack
2. The user mode registers for task t are saved to the current PCB

stage-2 Load the Next Context

作用:
1. transferring the PCB for t‘ into the banked user mode registers
2. The IRQ stack is restored to the original setting before entering the IRQ handler

Device Drive Framework(DDF)

DDF通过SWI instructions实现。DDF通过避免应用直接访问hardware来保护操作系统,and provide a uniform standard interface for tasks.If a task wanna to access a device ,it must first obtain a unique indentification number(UID).UID一般用于确定没有其他任务访问同一个设备。
SWI指令能作为从非特权模式切换到特权模式的一种方法。(p400图演示任务访问设备的流程)一旦SWI指令被执行,processor进入SVC模式,并且自动失能IRQ中断。

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在线阅读本书, , Over the last ten years, the ARM architecture has become one of the most pervasive architectures in the world, with more than 2 billion ARM-based processors embedded in products ranging from cell phones to automotive braking systems. A world-wide community of ARM developers in semiconductor and product design companies includes software developers, system designers and hardware engineers. To date no book has directly addressed their need to develop the system and software for an ARM-based system. This text fills that gap. This book provides a comprehensive description of the operation of the ARM core from a developer's perspective with a clear emphasis on software. It demonstrates not only how to write efficient ARM software in C and assembly but also how to optimize code. Example code throughout the book can be integrated into commercial products or used as templates to enable quick creation of productive software. The book covers both the ARM and Thumb instruction sets, covers Intel's XScale Processors, outlines distinctions among the versions of the ARM architecture, demonstrates how to implement DSP algorithms, explains exception and interrupt handling, describes the cache technologies that surround the ARM cores as well as the most efficient memory management techniques. A final chapter looks forward to the future of the ARM architecture considering ARMv6, the latest change to the instruction set, which has been designed to improve the DSP and media processing capabilities of the architecture., , * No other book describes the ARM core from a system and software perspective. * Author team combines extensive ARM software engineering experience with an in-depth knowledge of ARM developer needs. * Practical, executable code is fully explained in the book and available on the publisher's Website. * Includes a simple embedded operating system.

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