Once the boot mode is selected, the application software can modify the memory accessible in the code area.This modification is performed by programming the MEM_MODE bits in
the SYSCFG configuration register 1 (SYSCFG_CFGR1). Unlike Cortex? M3 and M4,the M0 CPU does not support the vector table relocation. For application code which is located in a different address than 0x0800 0000, some additional code must be added in order
to be ableto serve the application interrupts. A solution will be to relocateby software the vector table to the internal SRAM:
? Copy the vector table from the Flash (mapped at the base of theapplication load address) to the base address of the SRAM at 0x20000000.
? Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.
? Then once an interrupt occurs, the Cortex?-M0 processor will fetch the interrupt handler start address from the relocated vector table in SRAM, then it will jump to execute
the interrupt handler located in the Flash.
This operation should be done at the initialization phase of the application. Please refer to AN4065 and attached IAP code from www.st.com for