(UVM验证学习4) apb watchdog源码阅读

apb_defines.v

`define ARM_WDOG1A  7'b0000000
`define ARM_WDOG2A  7'b0000001

`define ARM_WDOGLA  7'b1100000

`define ARM_WDOGPA1 7'b1111111
`define ARM_WDOGPA2 7'b1111110


`define ARM_WDOGLOADA 3'b000
`define ARM_WDOGVALUEA 3'b001
`define ARM_WDOGCONTROLA 3'b010
`define ARM_WDOGCLEARA 3'b011
`define ARM_WDOGINTRAWA 3'b100
`define ARM_WDOGINTA 3'b101

`define ARM_WDOGLOCKA 3'b000 

`define ARM_WDOGTCRA 3'b000 
`define ARM_WDOGTOPA 3'b001

`define ARM_WPERIPHID4A 4'b0100
`define ARM_WPERIPHID5A 4'b0101
`define ARM_WPERIPHID6A 4'b0110
`define ARM_WPERIPHID7A 4'b0111
`define ARM_WPERIPHID0A 4'b0100
`define ARM_WPERIPHID1A 4'b1001
`define ARM_WPERIPHID2A 4'b1010
`define ARM_WPERIPHID3A 4'b0111

`define ARM_WPCELLID0A 4'b1100
`define ARM_WPCELLID1A 4'b1101
`define ARM_WPCELLID2A 4'b1110
`define ARM_WPCELLID3A 4'b1111 

apb_watchdog_frc.v

module apb_watchdog_frc (
    input wire         PCLK,        // apb clock
    input wire         PRESETn,     // apb reset
    input wire         PENABLE,     // apb enable
    input wire [4:2]   PADDR,       // apb address bus
    input wire         PWRITE,      // apb write
    input wire [31:0]  PWDATA,      // apb write data

    input wire         frc_sel,     // free running counter register select
    input wire         wdog_lock,   // lock register value
    input wire         WDOGCLK,     // wdog clk
    input wire         WDOGCLKEN,   // wdog clken
    input wire         WDOGRESn,    // wdog clk reset

    output wire        WDOGINT,     // frc interrupt
    output wire        WDOGRES,     // frc reset
    output reg  [31:0] frc_data     // read data output

);

    `include "apb_watchdog_defs.v"

    // submodule of wdog
    // contains:
    // * 32bit freee-running down-counter
    // * period load register
    // * control register  to enable reset and interrupt 
    // * interrupt status register
    // * lock register to prevent accidental write access
    // * interrupt and reset generation logic

    // control 
    wire         wdog_ctrl_en;     // ctrl write enable 
    reg   [1:0]  wdog_control;     //control register

    // load value
    wire         load_en;          //load write enable
    reg          load_en_reg;      //registered load enable 
    reg   [31:0] wdog_load;        //wdog_load register

    // 
    wire         load_tog_en;      // enable for load req toggle
    reg          load_req_tog_p;   // load req toggle PCLK domain
    reg          load_req_tog_w;   // load req toggle WDOGCLK domain
    wire         load_req_w;       // load req pulse WDOGCLK domian

    wire         count_stop;       // halt counter
    reg          count_stop_reg;   // registered count_stop

    reg   [15:0] nxt_count_low;    // count-1 [15:0]
    reg   [15:0] nxt_count_high;   // count-1 [31:16]
    reg          nxt_carry_0;      // decrement carry in
    reg          nxt_carry_1;      // decrement carry in
    wire  [1:0]  nxt_carry_mux;    // decrement carry in(muxed)
    reg   [1:0]  reg_carry;        // decrement carry in
    wire         carry_msb;        //  
    wire  [31:0] count_mux1;
    wire  [31:0] count_mux2;
    reg   [31:0] reg_count;        // current count
    wire  [31:0] count_read;
    wire  [31:0] high_count;

    wire         wdog_int_en;      // interrupt enable
    reg          wdog_int_en_reg;  // registered interrupt enable 
    wire         wdog_int_en_rise; // rising edge on interrupt enable 
    wire         wdog_res_en;      // reset enable
    reg          i_wdog_res;       // registered internal counter reset
    wire         nxt_wdog_res;     // next i_wdog_res value

    wire         int_clr_en;       // interrupt clear enable
    reg          int_clr_tog_p;    // int clear toggle...
    reg          int_clr_tog_w;
    wire         int_clr_pulse;
    wire         int_clr_w;
    reg          int_clr_reg_w;

    wire         nxt_wdog_ris;
    reg          wdog_ris;
    wire         read_wdog_ris;
    wire         wdog_mis;
    // free running counter需要考虑这些寄存器:LOAD,VALUE,CONTROL,CLEAR,INTCLR...
    // -------------------------------------------------------------------
    // control register
    // -------------------------------------------------------------------
    // PENABLE = 0 because need to be in SETUP state , not in ENABLE state
    // 思路和另外一个文件差不多,frc_sel=1,写操作,setup state,没有lock
    // 首先在SETUP state得知是否符合要求,然后按时钟周期采样输入数据,完成写操作
    assign wdog_ctrl_en = (PADDR == `ARM_WDOGCONTROLA) ?
                        (PWRITE & frc_sel & (~PENABLE) & (~wdog_lock)) : 1'b0;


    // write the ctrl_reg in the ENABLE state
    // because wdog_ctrl_en assert in SETUP state, then at next clk posedge
    // perform the PWDATA write, which is in the ENABLE state
    always @ (negedge PRESETn or posedge PCLK)
        begin : p_ctrl_seq
            if(~PRESETn)
                wdog_control[1:0] <= 2'b00;
            else
                if(wdog_ctrl_en)
                    wdog_control[1:0] <= PWDATA[1:0];
        end

    assign wdog_res_en = wdog_control[1];
    assign wdog_int_en = wdog_control[0];

    // 1. when the WDOGCLKEN=1 sample the wdog_int_en signal to