apb_watchdog(apb总线配置watchdog模块验证)寄存器模型

已于 2024-04-18 16:12:46 修改
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文章标签： fpga开发
于 2023-12-27 20:48:12 首次发布
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本文链接：https://blog.csdn.net/m0_69999886/article/details/135246043
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        以上的两篇文章，完成了对其测试点的提取以及验证工作(覆盖率会后面一篇文章写)，接下来的文章完成寄存器模型的编写以及寄存器模型对DUT内部寄存器的配置。

        使用寄存器模型完成对DUT内寄存器的配置分为以下几个步骤

  • 编写寄存器模型
  • 编写reg2bus_adapter
  • 编写virtual sequencer

一、寄存器模型、adapter编写

        寄存器模型的具体编写流程白皮书中很详细，以watchdog内的寄存器举个栗子~

//WDOGLOAD_reg
class reg_wdogload extends uvm_reg;
    uvm_reg_field LOADVAL;

    `uvm_object_utils(reg_wdogload)

    function new(string name="reg_wdogload");
        super.new(name,32,UVM_NO_COVERAGE);
    endfunction

    virtual function void build();
    this.LOADVAL=uvm_reg_field::type_id::create("LOADVAL",,get_full_name());
    this.LOADVAL.configure(this,32,0,"RW",0,'hFFFFFFFF,1,0,0);
    endfunction

endclass

        对于寄存器内有多个域的，依照白皮书上列出的参数编写即可。

//WDOGCONTROL_reg
class reg_wdogcontrol extends uvm_reg;
    uvm_reg_field RESEN;
    uvm_reg_field INTEN;

    `uvm_object_utils(reg_wdogcontrol)
 
    function new(string name="reg_wdogcontrol");
        super.new(name,32,UVM_NO_COVERAGE);
    endfunction

    virtual function void build();
    this.RESEN=uvm_reg_field::type_id::create("RESEN",,get_full_name());
    this.RESEN.configure(this,1,1,"RW",0,'h0,1,0,0);
    this.INTEN=uvm_reg_field::type_id::create("INTEN",,get_full_name());
    this.INTEN.configure(this,1,0,"RW",0,'h0,1,0,0);
    endfunction
endclass

        watchdog内部寄存器较多，如果手写，即使是复制粘贴改数据，也是一件繁琐的工作，可以利用ralgen脚本生成UVM寄存器模型。

        reg2bus_adapter转换器功能是实现寄存器模型级到总线级的信息转换，需定义好两个函数

  • reg2bus: 将寄存器模型通过sequence发出的uvm_reg_bus_op型变量转换成总线类型transaction级别
  • bus2reg: 当监测到总线上有操作时，将收集来的trasaction转换成寄存器模型能够接受的形式

        reg2bus_adapter编写方式和白皮书类似。

        寄存器模型、转换器编写完成后，其大致框架如图

        前门访问分为读和写两种，不管是哪种操作，寄存器模型都会通过sequence产生一个uvm_reg_bus_op的变量，此变量中存储着操作类型（读还是写）和操作的地址，如果是写操作，还需要有写入的数据。这个变量中的信息经过adapter转换后交给sequencer，sequencer交给driver。如果需要读取数据的话，driver可以获取到PRDATA，将此值放入到sequencer获取的transaction中，此transaction中就会有读取的值，经过adapter的传递，可被寄存器模型获取。

        virtual_sequencer编写完毕后，在base_test中将virtual_sequencer中的reg_model以及sequencer指向实际，并完成相关例化工作以及adapter的挂载，便可以在sequence中使用virtual_sequencer调用两者完成测试。

二、ral_interrupt_test 中断信号产生测试

        寄存器default值检测编写较为繁琐，略...与之前流程类似    

    virtual task body();
     uvm_status_e status;
    uvm_reg_data_t value;

    p_sequencer.wr.WDOGLOCK.set(32'h1ACCE551);
    p_sequencer.wr.WDOGLOAD.set(32'h2f);
    p_sequencer.wr.WDOGCONTROL.set(32'h1);
    //update
    p_sequencer.wr.WDOGLOCK.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGLOAD.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGCONTROL.update(status,UVM_FRONTDOOR);

while(1)begin
    @(posedge tb_top.WDOGCLK);
    p_sequencer.wr.WDOGVALUE.read(status,value,UVM_FRONTDOOR);
    `uvm_info("ral_interrupt_sequence",$sformatf("WDOGVALUE:%0h",value),UVM_LOW)
    if(tb_top.dut.WDOGINT==1)
    //if(value==0)
        break;
    end
     `uvm_info("ral_interrupt_sequence",$sformatf("WDOGINT %0h INTERRUPT RISE,",tb_top.dut.WDOGINT),UVM_LOW);

  endtask

   同样的流程，解锁寄存器写入权限，计数寄存器初始值设置为32‘h2f。     

UVM_INFO ../env/wdog_driver.sv(19) @ 0: uvm_test_top.env.agt.drv [wdog_driver] main_phase Enter...
UVM_INFO ../env/wdog_monitor.sv(24) @ 0: uvm_test_top.env.agt.mon [wdog_monitor] main_phase Enter...
UVM_INFO ../env/wdog_scoreboard.sv(29) @ 0: uvm_test_top.env.scb [wodg_scorebaord] main_phase Enter...
UVM_INFO ../test/ral_interrupt_test.sv(18) @ 0: uvm_test_top [ral_interrupt_test] main_phase Enter...
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 136000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2f
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 186000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2e
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 236000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2d
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 286000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2c
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 336000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2b
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 386000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2a
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 436000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:29
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 486000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:28
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 536000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:27
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 586000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:26
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 636000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:25
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 686000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:24
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 736000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:23
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 786000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:22
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 836000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:21
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 886000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:20
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 936000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1f
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 986000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1e
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1036000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1d
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1086000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1c
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1136000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1b
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1186000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1a
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1236000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:19
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1286000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:18
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1336000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:17
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1386000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:16
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1436000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:15
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1486000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:14
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1536000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:13
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1586000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:12
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1636000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:11
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1686000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:10
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1736000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:f
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1786000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:e
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1836000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:d
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1886000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:c
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1936000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:b
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 1986000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:a
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2036000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:9
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2086000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:8
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2136000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:7
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2186000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:6
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2236000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:5
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2286000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:4
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2336000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:3
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2386000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2436000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:1
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2486000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:0
UVM_INFO ../seq/ral_interrupt_sequence.sv(28) @ 2536000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGVALUE:2f
UVM_INFO ../seq/ral_interrupt_sequence.sv(33) @ 2536000: uvm_test_top.v_seqr@@seq [ral_interrupt_sequence] WDOGINT 1 INTERRUPT RISE,
SvtTestEpilog:------------------------ Passed---------------


--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   65
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[UVMTOP]     1
[base_test]     3
[ral_interrupt_sequence]    50
[ral_interrupt_test]     1
[wdog_agent]     3
[wdog_driver]     1
[wdog_env]     2
[wdog_monitor]     1
[wdog_scoreboard]     1
[wodg_scorebaord]     1
$finish called from file "/eda/vcs_vO-2018.09-SP2/vcs/O-2018.09-SP2/etc/uvm-1.1/base/uvm_root.svh", line 439.
$finish at simulation time             12536000

---------------------------------------------------------------------------
VCS Coverage Metrics: during simulation line, cond, FSM, branch, tgl was monitored
---------------------------------------------------------------------------
           V C S   S i m u l a t i o n   R e p o r t 
Time: 12536000 ps
CPU Time:      0.430 seconds;       Data structure size:   0.5Mb
Wed Dec 27 17:58:40 2023

计数寄存器WDOGVALUE初始值设置为2f。sequence的写法很多，上面只是其中一种。

三、ral_intclr_test中断信号清除测试

        用write或者set/update命令向WDOGINTCLR寄存器写入有效数值

UVM_INFO ../test/ral_intclr_test.sv(18) @ 0: uvm_test_top [ral_intclr_test] main_phase Enter...
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 136000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:10
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 186000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:f
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 236000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:e
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 286000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:d
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 336000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:c
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 386000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:b
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 436000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:a
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 486000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:9
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 536000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:8
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 586000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:7
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 636000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:6
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 686000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:5
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 736000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:4
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 786000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:3
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 836000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:2
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 886000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:1
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 936000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:0
UVM_INFO ../seq/ral_intclr_sequence.sv(28) @ 986000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGVALUE:10
UVM_INFO ../seq/ral_intclr_sequence.sv(33) @ 986000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGINT 1 INTERRUPT RISE,
ENABLE INTCLR...
UVM_INFO ../seq/ral_intclr_sequence.sv(42) @ 1015000: uvm_test_top.v_seqr@@seq [ral_intclr_sequence] WDOGINT 0 INTERRUPT DOEN
SvtTestEpilog:------------------------ Passed---------------


--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   35
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[UVMTOP]     1
[base_test]     3
[ral_intclr_sequence]    20
[ral_intclr_test]     1
[wdog_agent]     3
[wdog_driver]     1
[wdog_env]     2
[wdog_monitor]     1
[wdog_scoreboard]     1
[wodg_scorebaord]     1
$finish called from file "/eda/vcs_vO-2018.09-SP2/vcs/O-2018.09-SP2/etc/uvm-1.1/base/uvm_root.svh", line 439.
$finish at simulation time             11015000

---------------------------------------------------------------------------
VCS Coverage Metrics: during simulation line, cond, FSM, branch, tgl was monitored
---------------------------------------------------------------------------

 Coverage status: End of All Coverages ...

           V C S   S i m u l a t i o n   R e p o r t 
Time: 11015000 ps
CPU Time:      0.490 seconds;       Data structure size:   0.5Mb
Wed Dec 27 18:31:16 2023

        将初始值改小了一点，要不打印结果太重复了。配置完WDOGINTCLR后，WDOGINT中断信号被清除。

四、ral_inter_test watchdog 集成测试模式

        其实都是重复第一种方法的步骤，只是换了寄存器模型去配置。

    virtual task body();
    wdog_transaction trans;
    uvm_status_e status;
    uvm_reg_data_t value;

    p_sequencer.wr.WDOGLOCK.set(32'h1ACCE551);
    p_sequencer.wr.WDOGITCR.set(32'h1);
    `ifdef ITOP_3
    $display("Enter ITOP_3...");
    p_sequencer.wr.WDOGITOP.set(32'h3);
    //update
    p_sequencer.wr.WDOGLOCK.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITCR.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITOP.update(status,UVM_FRONTDOOR);

while(1)begin
    @(posedge tb_top.PCLK);
    if(tb_top.dut.WDOGINT==1&&tb_top.dut.WDOGRES==1)
    //if(value==0)
        break;
    end
//    p_sequencer.wr.WDOGMIS.read(status,value,UVM_FRONTDOOR);
//    `uvm_info("ral_intertest_sequence",$sformatf("WDOGMIS %0h",value),UVM_LOW)
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGINT %0h INTERRUPT RISE,",tb_top.dut.WDOGINT),UVM_LOW);
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGRES %0h RESET RISE,",tb_top.dut.WDOGRES),UVM_LOW);
 `endif

 `ifdef ITOP_2
    $display("Enter ITOP_2...");
     p_sequencer.wr.WDOGITOP.set(32'h2);
    //update
    p_sequencer.wr.WDOGLOCK.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITCR.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITOP.update(status,UVM_FRONTDOOR);

while(1)begin
    @(posedge tb_top.PCLK);
    if(tb_top.dut.WDOGINT==1&&tb_top.dut.WDOGRES==0)
    //if(value==0)
        break;
    end
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGINT %0h INTERRUPT RISE,",tb_top.dut.WDOGINT),UVM_LOW);
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGRES %0h RESET DOWN",tb_top.dut.WDOGRES),UVM_LOW);
 `endif

 //ITOP_1
 `ifdef ITOP_1
    $display("Enter ITOP_1...");
     p_sequencer.wr.WDOGITOP.set(32'h1);
    //update
    p_sequencer.wr.WDOGLOCK.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITCR.update(status,UVM_FRONTDOOR);
    p_sequencer.wr.WDOGITOP.update(status,UVM_FRONTDOOR);

while(1)begin
    @(posedge tb_top.PCLK);
    if(tb_top.dut.WDOGINT==0&&tb_top.dut.WDOGRES==1)
    //if(value==0)
        break;
    end
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGINT %0h INTERRUPT DOWN,",tb_top.dut.WDOGINT),UVM_LOW);
     `uvm_info("ral_intertest_sequence",$sformatf("WDOGRES %0h RESET RISE,",tb_top.dut.WDOGRES),UVM_LOW);
 `endif


  endtask

        这个sequence的写法同样很多，我抛砖引玉昂~

UVM_INFO ../test/ral_inter_test.sv(18) @ 0: uvm_test_top [ral_inter_test] main_phase Enter...
Enter ITOP_3...
UVM_INFO ../seq/ral_intertest_sequence.sv(35) @ 85000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGINT 1 INTERRUPT RISE,
UVM_INFO ../seq/ral_intertest_sequence.sv(36) @ 85000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGRES 1 RESET RISE,
Enter ITOP_2...
UVM_INFO ../seq/ral_intertest_sequence.sv(53) @ 105000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGINT 1 INTERRUPT RISE,
UVM_INFO ../seq/ral_intertest_sequence.sv(54) @ 105000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGRES 0 RESET DOWN
Enter ITOP_1...
UVM_INFO ../seq/ral_intertest_sequence.sv(72) @ 125000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGINT 0 INTERRUPT DOWN,
UVM_INFO ../seq/ral_intertest_sequence.sv(73) @ 125000: uvm_test_top.v_seqr@@seq [ral_intertest_sequence] WDOGRES 1 RESET RISE,
SvtTestEpilog:------------------------ Passed---------------


--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   21
UVM_WARNING :    0
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[RNTST]     1
[UVMTOP]     1
[base_test]     3
[ral_inter_test]     1
[ral_intertest_sequence]     6
[wdog_agent]     3
[wdog_driver]     1
[wdog_env]     2
[wdog_monitor]     1
[wdog_scoreboard]     1
[wodg_scorebaord]     1
$finish called from file "/eda/vcs_vO-2018.09-SP2/vcs/O-2018.09-SP2/etc/uvm-1.1/base/uvm_root.svh", line 439.
$finish at simulation time             10125000

---------------------------------------------------------------------------
VCS Coverage Metrics: during simulation line, cond, FSM, branch, tgl was monitored
---------------------------------------------------------------------------

 Coverage status: End of All Coverages ...

           V C S   S i m u l a t i o n   R e p o r t 
Time: 10125000 ps
CPU Time:      0.480 seconds;       Data structure size:   0.5Mb
Wed Dec 27 20:01:38 2023

 以上是寄存器模型大致的一个操作，只写了主要部分...

后续应该还要补充，总感觉落下点啥......

下一篇章写如何用APB VIP来验watchdog模块 

        

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