FPGA Verilog 串行转并行（1位-16位）带tb

fpga Verilog 串行转并行（1位-16位）带tb

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使用步骤

代码如下（示例）：将所有变量输出是为了方便仿真

module one_sixteen(
	input clk,
	input rst_n,
	input din,
	input start,//检测帧头标志
	output reg   [15:0] data,//缓存数据
	output reg   [5:0]  cnt,//计数器
	output reg   [15:0] dout//实际数据
);


//输入进来之后一直进行移位 与start标志无关
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
   	data <= 16'b0;
		end
   else begin
   	data <= {data[14:0], din};	//低位先赋值
   	end
   end
	
//start标志决定cnt的增加 当cnt==16 cnt归为1 注意写法要写成000001
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
   	cnt <= 6'b0;
		end
   else if (start == 1 && cnt < 16) begin
   	cnt <= cnt + 1'b1;	
   	end
   else begin
		cnt <= 6'b000001;
		end
   end	
	
//当cnt=16的时候把想要的值取出来
always @(posedge clk or negedge rst_n) begin
   if (rst_n == 1'b0) begin
   	dout <= 16'b0;
		end
   else if(cnt == 6'b010000)begin
   	dout <= data;	//低位先赋值
   	end
   else begin 
		dout <= dout;
	end
   end	

endmodule

tb仿真文件

代码如下（示例）：

`timescale 1 ns/ 1 ps
module one_sixteen_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg din;
reg rst_n;
reg start;
// wires                                               
wire [15:0]  dout;
wire   [15:0] data;
wire  [5:0]  cnt;

integer j;
// assign statements (if any)                          
one_sixteen i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.din(din),
	.dout(dout),
	.rst_n(rst_n),
	.data(data),
	.cnt(cnt),
	.start(start)
);
initial begin
  clk <= 1'b0;
  rst_n <= 1'b0;
  start = 1;

#5
  rst_n <= 1'b1;
  
  
#100000
  start <= 1'b0;
#500
  start <= 1'b1;
end

always #100 clk =~ clk;  //5m

initial
begin
	#5 din <=1;
	for(j = 0;j<10000;j = j+1)
	begin
		#200 din = 0;     
		#200 din = 1;
		#200 din = 0;
		#200 din = 1;

		#200 din = 0;
		#200 din = 1;
		#200 din = 0;
		#200 din = 1;

		#200 din = 0;
		#200 din = 1;
		#200 din = 0;
		#200 din = 1;

		#200 din = 0;
		#200 din = 1;
		#200 din = 0;
		#200 din = 1;
		end
end

endmodule

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总结

可以通过仿真

码字不易 留下你的足迹！