可输入初始值得60进制计数器

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    09:04:55 08/13/2015 
// Design Name: 
// Module Name:    Count60 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 同步60进制计数器，可输入初始计数值
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module Count60(clk,rst_n,data_in,c_in,ctrol,q_out,c_out
    );
//***********************
//delay declation
//***********************
parameter U_DLY=1;
//***********************
//input port
//***********************
input 		clk;   //100mhz
input 		rst_n; //active low
input [5:0]     data_in;
input 		c_in;
input	        ctrol; //ctrol=1 count from data_in;
		       //ctrol=0 count from 0;

//***********************
//output port
//***********************
output [5:0] q_out;
output	     c_out; 		

//***********************
//wire or reg declation
//***********************
reg [5:0]	 q_out;
reg 		 c_out;