60bit计数器

module counter_60bit
( clk , 
clear ,
dl ,
dh ,
en ,
load ,
ql ,
qh ,
cout);

input clk , clear , en , load;
input [3:0] dl , dh;
output [3:0] ql , qh;
output cout;

reg [3:0] ql;
reg [3:0] qh;

always@( posedge clk or negedge clear )
	if( !clear )
		begin
			ql <= 0;
			qh <= 0;
		end
	else if( load )
		begin
			ql <= dl;
			qh <= dh;
		end
	else if( en )
		if( ql == 4'h9 )
			begin
				ql <= 0;
				if( qh == 4'h5 )
					qh <= 0;
				else
					qh <= qh + 1;
			end
		else 
			ql <= ql + 1;

assign cout = ( en == 1 && ql == 4'h9 && qh == 4'h5 ) ? 1'b1 : 1'b0;

endmodule

testbench文件：

`timescale 1 ns/ 1 ps
module counter_60bit_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clear;
reg clk;
reg [3:0] dh;
reg [3:0] dl;
reg en;
reg load;
// wires                                               
wire cout;
wire [3:0]  qh;
wire [3:0]  ql;

// assign statements (if any)                          
counter_60bit i1 (
// port map - connection between master ports and signals/registers   
	.clear(clear),
	.clk(clk),
	.cout(cout),
	.dh(dh),
	.dl(dl),
	.en(en),
	.load(load),
	.qh(qh),
	.ql(ql)
);

always 
    begin
        clk<=1;#15;
        clk<=0;#15;
    end
	 
//清零，先清零让ql，qh等于0，再启动
initial
    begin
        clear=0;#30;
        clear=1;
    end
	 
	 
//使能信号
initial
    begin
        en=0;#200;
        en=1; 
    end
	 
endmodule  

仿真结果：