2021-06-04

Verilog HDL 测试模块
代码：
module p2s(data_in,clock,reset,load, data_out,done);
input [3:0] data_in;
input clock, reset ,load;
output data_out;
output done;
reg done;
reg [3:0]temp;
reg [3:0]cnt;
always @(posedge clock or posedge reset )
begin
if(reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if(cnt3)
begin
temp <= {temp[2:0],1’b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1’b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_out=(done1)?1’bz:temp[3];
endmodule
结果如图：