include/configs/sun4i.h
#define CONFIG_NR_DRAM_BANKS 2
#define SDRAM_BANK_SIZE (512UL << 20UL)/* 512 MB */
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
board/allwinner/a10-evb/a10-evb.c
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start=PHYS_SDRAM_1;
gd->bd->bi_dram[0].size=PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].start=PHYS_SDRAM_2;
gd->bd->bi_dram[1].size=PHYS_SDRAM_2_SIZE;
}
int dram_init(void)
{
gd->ram_size =get_ram_size((long*)PHYS_SDRAM_1,PHYS_SDRAM_1_SIZE)
+ get_ram_size((long*)PHYS_SDRAM_2,PHYS_SDRAM_2_SIZE);
return 0;
}
arch/arm/cpu/armv7/sunxi/dram.c
static inline void dram_config_type(structsunxi_dram_reg*dram)
{
sr32(&dram->dcr,0,1,DCR_TYPE_DDR3);
sr32(&dram->dcr,1,2,DCR_IO_WIDTH_16);
sr32(&dram->dcr,3,3,DCR_CHIP_DENSITY_4Gb); /*DCR_CHIP_DENSITY_4Gb=1G;DCR_CHIP_DENSITY_2Gb=512Mb*/
sr32(&dram->dcr,6,3,DCR_BUS_WIDTH_32);
sr32(&dram->dcr,10,2,DCR_ONE_RANK);
sr32(&dram->dcr,12,1,DCR_CMD_ON_ALL_RANKS);
sr32(&dram->dcr,13,2,DCR_INTERLEAVE_MODE);
}