作者:gooogleman@foxmail.com // 以后有时间再整理成一份好的技术文档,现在自己先预留着先。
{.clk = {
.name = "sclk_fimd",
.id = -1,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group2,
// #define S5P_CLK_SRC1 S5P_CLKREG(0x204)
// #define S5P_CLK_DIV1 S5P_CLKREG(0x304)
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
/* fixed clock source: hclk */
cfg = readl(ctrl->regs + S3C_VIDCON0);
cfg &= ~(S3C_VIDCON0_CLKSEL_MASK | S3C_VIDCON0_CLKVALUP_MASK |
S3C_VIDCON0_VCLKEN_MASK | S3C_VIDCON0_CLKDIR_MASK);
cfg |= (S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_VCLKEN_NORMAL |
S3C_VIDCON0_CLKDIR_DIVIDED);