ALU设计实验 alu_tb.v代码

`timescale  1ns / 1ps
`include "alu.v"
module alu_tb;
	parameter width=32;
	wire [width-1:0] r;
	wire z;
	reg [width-1:0] a,b;
	reg [3:0] aluc;

	initial begin
    #2 a=32'hffffff00;b=32'h200;
    aluc[3:0] = 4'b0011;
    #2 a=32'heeeeeeee;b=32'h55555555;
    for(aluc=0;aluc<=15;aluc=aluc+1) #2;

     #2 a=32'hffffff01;b=32'h200;
    end;
    alu m(.a(a),.b(b),.aluc(aluc),.r(r),.z(z));
	initial begin 
        $dumpfile("test.vcd");
        $dumpvars;
        $monitor ("%g\t %b %b %b %b %b",$time,a,b,aluc,r,z);
        #50 $finish;
    end
endmodule