c6000PLL编程

  /* Initialize PLL Registers */        
  /* Put PLL in bypass */
 PLL_bypass();
 PLLdelay(20);
 
  /* Reset PLL */
 PLL_reset();
 PLLdelay(20);
 
  /* Set main multiplier/divisor */
    PLL_RSET(PLLM,18);      //25MHz×18=450MHz
    PLL_RSET(PLLDIV0,PLL_PLLDIV0_RMK(1,0));  //450MHz/1=450MHz
    PLL_RSET(OSCDIV1,PLL_OSCDIV1_RMK(1,0));  //25MHz/1=25MHz(CLKOUT3)
  
     /* Set DSP clock */
    PLL_RSET(PLLDIV1,PLL_PLLDIV1_RMK(1,1));  //450MHz/2=225MHz
    PLLdelay(20);
  
     /* Set peripheral clock */
    PLL_RSET(PLLDIV2,PLL_PLLDIV2_RMK(1,3));  //450MHz/4=112.5MHz(CLKOUT2)
    PLLdelay(20);
   
     /* Set EMIF clock */
    PLL_RSET(PLLDIV3,PLL_PLLDIV3_RMK(1,4));  //450MHz/5=90MHz(ECLKOUT)
    PLLdelay(20);
   
     /* Take PLL out of reset */
    PLL_deassert();
    PLLdelay(1500);
   
     /* Enalbe PLL */
    PLL_enable();
    PLLdelay(20);