module breathe(
input clk,
output reg led
);
reg [26:0]cnt = 1'b0;
always @(posedge clk)
begin
cnt <= cnt + 1'b1;
if(cnt[15:6]>cnt[25:16])begin
led <= cnt[26];
end else begin
led <= ~cnt[26];
end
end
endmodule
笔者的clk是50M