实验一与门

最新推荐文章于 2022-06-01 00:03:27 发布

hedafighter2011

最新推荐文章于 2022-06-01 00:03:27 发布

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本文链接：https://blog.csdn.net/hedafighter2011/article/details/8822124

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library ieee;  
use ieee.std_logic_1164.all;  
  
entity wss1 is  
  
port   
  (  
     a,b: in std_logic;  
      y:  out std_logic  
  );  
  
end entity;  
  
architecture rtl of  wss1 is  
  
begin   
  
    y   <=a   and   b;  
  
end rtl;  

library ieee;
use ieee.std_logic_1164.all;

entity wss1 is

port 
  (
     a,b: in std_logic;
      y:  out std_logic
  );

end entity;

architecture rtl of  wss1 is

begin 

    y   <=a   and   b;

end rtl;