-- Quartus VHDL Template
-- Clearable loadable enablable counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY adder4_2 IS
PORT
(
a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ci : IN STD_LOGIC;
s : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
co : OUT STD_LOGIC
);
END adder4_2;
ARCHITECTURE rtl OF adder4_2 IS
signal aa,bb,ss : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
aa <= '0' & a;
bb <= '0' & b;
ss <= aa + bb + ci;
s <= ss(3 DOWNTO 0);
co <= ss(4);
END rtl;
实验四 四位加法器实验adder4_2
最新推荐文章于 2023-10-09 15:51:04 发布