LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lcd12864 IS
PORT(
CLK: IN STD_LOGIC;
ROM_DATA: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RS,RW,CS1,CS2,E: OUT STD_LOGIC;
ADDRESS: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;
ARCHITECTURE BEHAV OF lcd12864 IS
TYPE STATES IS(ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7,
ST8,ST9,ST10,ST11,ST12,ST13,ST14,ST15); --状态定意
SIGNAL PRE_STATE,NEXT_STATE:STATES;
SIGNAL DATALOCK,EN,RST1:STD_LOGIC;
SIGNAL ADDR:INTEGER RANGE 0 TO 65:=0;
SIGNAL XPAGE:STD_LOGIC_VECTOR(7 DOWNTO 0):="10111000";
SIGNAL YADDR:STD_LOGIC_VECTOR(7 DOWNTO 0):="01000000";
BEGIN
CLOCK:PROCESS(CLK) --将时钟进行分频
VARIABLE CONT:INTEGER RANGE 0 TO 20;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
CONT:=CONT+1;
IF CONT = 12 THEN DATALOCK<='0';CONT:=0;
ELSIF CONT = 9 THEN
DATALOCK<='1';
END IF;
END
FPGA驱动12864液晶
最新推荐文章于 2021-10-12 17:47:40 发布
该博客详细介绍了如何使用FPGA来驱动12864液晶显示器,通过定义状态机并设置相应的控制信号,实现液晶的初始化、清屏以及数据显示功能。通过时钟分频和数据锁存机制确保信号的正确传输。
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