lcd12864历程C语言程序,FPGA学习历程——（五）LCD12864操作

module LCD_MODULE

(

input wClock,

input wReset,

output wCS,

output wA0,

output wSCK,

output wSD

);

wire wBusy;

reg rWE;

reg [7:0] rData;

SPI_MODULE SPI_INS

(

.wClock(wClock),

.wReset(wReset),

.wBusy(wBusy),

.wEnable(1),

.wWE(rWE),

.wDATA(rData),

.wCS(wCS),

.wSCK(wSCK),

.wMOSI(wSD)

);

reg [7:0] rSTATE;

reg [3:0] rSubSTATE;

reg rA0;

assign wA0=rA0;

always @(posedge wClock or negedge wReset)

if(!wReset) begin

rSTATE<=8'H00;

rWE<=1'B1;

rA0<=1'B0;

end

else begin

case(rSTATE)

8'H00: begin

rSubSTATE<=4'H0;

rSTATE<=8'H01;

end

8'H01: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HAF;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H02;

end

end

endcase;

end

8'H02: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'H40;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H03;

end

end

endcase;

end

8'H03: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HA6;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H04;

end

end

endcase;

end

8'H04: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HA0;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H05;

end

end

endcase;

end

8'H05: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HC8;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H06;

end

end

endcase;

end

8'H06: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HA4;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H07;

end

end

endcase;

end

8'H07: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HA2;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H08;

end

end

endcase;

end

8'H08: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'H24;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H09;

end

end

endcase;

end

8'H09: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B1;

rData<=8'H2F;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H0A;

end

end

endcase;

end

8'H0A: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'H81;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H0B;

end

end

endcase;

end

8'H0B: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'H24;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H0C;

end

end

endcase;

end

8'H0C: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HA6;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H0D;

end

end

endcase;

end

8'H0D: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B0;

rData<=8'HB0;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

rSTATE<=8'H0E;

end

end

endcase;

end

8'H0E: begin

case(rSubSTATE)

4'H0:begin

rWE<=1'B0;

rA0<=1'B1;

rData<=8'HAA;

rSubSTATE=4'H1;

end

4'H1:begin

rWE<=1'B1;

if(wBusy) rSubSTATE=4'H2;

end

4'H2:begin

if(!wBusy)begin

rSubSTATE<=4'H0;

end

end

endcase;

end

endcase;

end

endmodule