PACE DESIGH名词解释

Pinout and Area Constraints Editor (PACE™) is an interactive graphical application that you can use as follows:

• To view and edit location constraints for I/Os and global logic

• To view and create area constraints for logic in your design

• To determine resource requirements of your design

• To determine resource layout of  your target device

Use PACE during initial design entry, or after consolidation of a design into a netlist file. For initial design entry, PACE reads and writes VHDL and Verilog files, limited to I/O definitions. For consolidated netlists, PACE reads the NGD file. In both cases, PACE reads and writes user constraint files (UCFs).

PACE Files

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Input Files

PACE™ reads in the following files:

• NGD

The Native Generic Design (NGD) file is the design file output from NGDBuild.

• UCF

The User Constraints file (UCF) is an ASCII file specifying constraints on the logical design. These constraints affect the way the logical design is implemented in the target device.

• LFP

The Logical Floorplan file (LFP) file associates a design file with a UCF file and  contains grouping and color information applied to your design.

• VHDL

The VHDL top-level file (VHD) represents the top-level module in the design with I/O ports. PACE understands only data about I/O pins in this file.

• Verilog

The Verilog top-level file (V) represents the top-level module in the design with I/O ports. PACE understands only data about I/O pins in this file.

• CSV

Excel Comma Separated Value (CSV) file is a comma-separated list file, which can be imported into PACE. This file may be used as a means of transferring I/O data to or from external tools. This file is not allowed on the command line.

Output Files

PACE generates the following output files:

• LFP

The Logical Floorplan File (LFP) file associates a design file with a UCF file and contains grouping and color information applied to your design.

• UCF

PACE writes a UCF file. This allows the floorplan to become part of your design source archives. I/O and area constraints defined in PACE are saved in the UCF.

• VHDL

You can save the top-level VHDL from PACE if you are creating a new design. Because PACE is not a full VHDL editor, only I/O data can be written into this file.

• Verilog

You can save the top-level Verilog from PACE if you are creating a new design. Because PACE is not a full Verilog editor, only I/O data can be written into this file.

• CSV

You can export a CSV file that contains all the design I/Os and their properties.