Top-level HDL Flow

You can use PACE™ for pin assignment at an early stage of the design cycle by starting with a top-level HDL design, as described in the following procedure:

1. Select a top-level HDL (VHDL or Verilog) file and specify a part type.

2. PACE parses the HDL file and extracts the I/O ports, which are then displayed in the Design Browser under the I/O Pins folder.

3. Make pin assignments and apply I/O constraints, such as IOStandard and Slew.

4. Save the Constraints.

5. PACE creates a new UCF that is used as input to NGDBuild.

6. The remainder of the Xilinx implementation flow is completed.