Amlogic Linux系列（一）S912盒子刷Khadas ubuntu系统

打算学习一下Amlogic Linux系统，目前已知的amlogic Linux系统包括

1.官方的buildroot（没有技术资料，只支持A311D/S905D3)

2.khadas ubuntu (开源，只对vim系列开发板技术支持）：

KVM1-S905X

KVM2-S912

KVM3-A311D

手上有一块amlogic S912的盒子一直没用，buildroot是没法用了，准备将KVM2的ubuntu系统移植到这块板子上，并移植后相关驱动，并做后续的功能测试

这块板子的基本配置：

S912+LPDDR3+32G带RTC数码管

目录

一.安装环境及编译

二.相关修改

---

一.安装环境及编译

安装相关编译环境

sudo apt-get install git make lsb-release qemu-user-static

下载代码

mkdir -p ~/project/khadas
$ cd ~/project/khadas
$ git clone --depth 1 https://github.com/khadas/fenix
$ cd fenix

目录说明

archives/:一些存档

build/:包括编译的img、uboot、kernel代码等

config/:包括更具体的执行脚本，如编译uboot/kernel等

docs/:文档

downloads/:包括packages下载或编译后的文件

env/:包括环境脚本

packages/:包括第三方包的编译脚本

scripts/：包括编译脚本

编译，S912对应的是kvm2，选择kvm2，第一次选择编译server，然后选择emmc版本

source env/setenv.sh

编译后的img位于build\images目录下。

二.相关修改

因为实际的板子与vim2的板子有所区别，因此编译的固件是没办法使用的，需要做一下修改，我手上的板子是lpddr3的，khadas sdk是不支持的，因此需要对uboot进行相关修改。

1.去掉kvm2 开机检测

+++ b/board/khadas/configs/kvim2.h
@@ -318,10 +318,7 @@
             "run upgrade_check;"\
             "run init_display;"\
             "run storeargs;"\
-            "run combine_key;" \
             "run upgrade_key;" \
-            "run vim2_check;" \
-            "run wol_init;"\
             "forceupdate;" \
             "run switch_bootmode;"

2.支持lpddr3

+++ b/board/khadas/configs/kvim2.h
 /* ddr */
 #define CONFIG_DDR_AUTO_DTB             1
-#define CONFIG_DDR_SIZE                                        0 //MB //0 means ddr size auto-detect
-#define CONFIG_DDR_CLK                                 912  //MHz, Range: 384-1200, should be multiple of 24
+#define CONFIG_DDR_SIZE                                        3072 //MB //0 means ddr size auto-detect
+#define CONFIG_DDR_CLK                                 744  //MHz, Range: 384-1200, should be multiple of 24
 #define CONFIG_DDR4_CLK                                        1008  //MHz, for boards which use different ddr chip
 #define CONFIG_NR_DRAM_BANKS                   1
 /* DDR type setting
@@ -348,17 +345,17 @@
  *    CONFIG_DDR_TYPE_DDR3     : DDR3
  *    CONFIG_DDR_TYPE_DDR4     : DDR4
  *    CONFIG_DDR_TYPE_AUTO     : DDR3/DDR4 auto detect */
-#define CONFIG_DDR_TYPE                                        0x0F /* CONFIG_DDR_TYPE_AUTO */
+#define CONFIG_DDR_TYPE                                        0x02 /* CONFIG_DDR_TYPE_AUTO */
 /* DDR channel setting, please refer hardware design.
  *    CONFIG_DDR0_RANK0        : DDR0 rank0
  *    CONFIG_DDR0_RANK01       : DDR0 rank0+1
  *    CONFIG_DDR0_16BIT        : DDR0 16bit mode
  *    CONFIG_DDR0_16BIT_2      : DDR0 16bit mode, 2ranks
  *    CONFIG_DDR_CHL_AUTO      : auto detect RANK0 / RANK0+1 */
-#define CONFIG_DDR_CHANNEL_SET                 0x0F /* CONFIG_DDR0_RANK01 */
+#define CONFIG_DDR_CHANNEL_SET                 0x03 /* CONFIG_DDR0_RANK01 */
 /* ddr functions */
 #define CONFIG_DDR_FULL_TEST                   0 //0:disable, 1:enable. ddr full test
-#define CONFIG_CMD_DDR_D2PLL                   0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_D2PLL                   1 //0:disable, 1:enable. d2pll cmd
 #define CONFIG_CMD_DDR_TEST                            0 //0:disable, 1:enable. ddrtest cmd
 #define CONFIG_DDR_LOW_POWER                   0 //0:disable, 1:enable. ddr clk gate for lp
 #define CONFIG_DDR_ZQ_PD                               0 //0:disable, 1:enable. ddr zq power down
@@ -366,6 +363,12 @@
 #define CONFIG_DDR4_TIMING_TEST                        0 //0:disable, 1:enable. ddr4 timing test function
 #define CONFIG_DDR_PLL_BYPASS                  0 //0:disable, 1:enable. ddr pll bypass function
 
+/* lpddr3 config */
+#define CONFIG_LPDDR_REMAP_SET                 LPDDR_DIE_ROW_COL_R14_C10
+#define CONFIG_DDR_FUNC_LPDDR3_CA              1
+#define CONFIG_LPDDR3_CA_TRAINING_CA0  0
+#define CONFIG_LPDDR3_CA_TRAINING_CA1  2
+
 /* storage: emmc/nand/sd */
 #define        CONFIG_STORE_COMPATIBLE 1
 /*

2.修改board/khadas/kvim2/firmware/timing.c

diff --git a/board/khadas/kvim2/firmware/timing.c b/board/khadas/kvim2/firmware/timing.c
old mode 100644
new mode 100755
index e050268d3d..c133389d20
--- a/board/khadas/kvim2/firmware/timing.c
+++ b/board/khadas/kvim2/firmware/timing.c
@@ -103,8 +103,8 @@
 #define CONFIG_SOC_VREF    1+ (50+((50*48)/(48+480/(6+1)))) // 880/12  //(50+((50*48)/(48+160)))  //0//50+50*drv/(drv+odt)  (738/12) //0 //0  is auto --70 ---range 44.07---88.04   %
 #define CONFIG_DRAM_VREF  1+ (50+((50*37)/(37+48)))// 860/12 // 0// (810/12) // 0 //77 //0 //0  is auto ---70 --range -- 45---92.50    %
 #elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
-#define CONFIG_SOC_VREF  51
-#define CONFIG_DRAM_VREF 51
+#define CONFIG_SOC_VREF  51//(1+ (50+((50*48)/(48+480/(3+1)))))//51
+#define CONFIG_DRAM_VREF 51//(1+ (50+((50*53)/(53+120))))//51
 #else
 #define CONFIG_SOC_VREF  51
 #define CONFIG_DRAM_VREF 51
@@ -475,6 +475,21 @@ ddr_set_t __ddr_setting = {
 								[3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 30 << 25 ) ,
 								[4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
 	},
+#elif (CONFIG_LPDDR_REMAP_SET ==  LPDDR_DIE_ROW_COL_R14_C10)
+	.ddr0_addrmap			= {
+								[0]=( 5 |  6 << 5 |  7 << 10 |  8 << 15 |  9 << 20 | 10 << 25) ,
+								[1]=( 11| 30 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+								[2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+								[3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 29 << 25 ) ,
+								[4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+	},
+	.ddr1_addrmap			= {
+								[0]=( 5 |  6 << 5 |  7 << 10 |  8 << 15 |  9 << 20 | 10 << 25) ,
+								[1]=( 11| 30 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ) ,
+								[2]=( 17| 18 << 5 | 19 << 10 | 20 << 15 | 21<< 20 | 22 << 25 ) ,
+								[3]=( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 29 << 25 ) ,
+								[4]=( 31| 12 << 5 | 13 << 10 | 28 << 15 | 0 << 20 | 0 << 25 ) ,
+	},
 #endif /*CONFIG_LPDDR_REMAP_SET*/
 #else
 	.ddr0_addrmap			= {0},
@@ -500,7 +515,7 @@ ddr_set_t __ddr_setting = {
 							[3] = (20000 | (136 << 20)),
 							[4] = (1000 | (180 << 16)),
 							},  //PUB PTR0-3
-	.t_pub_odtcr			= 0x00030000,
+	.t_pub_odtcr			= 0x00010000,
 	.t_pub_mr				= {
 							(0X0 | (0X1 << 2) | (0X0 << 3) | (0X0 << 4) | (0X0 << 7) | (0X0 << 8) | (0X7 << 9) | (1 << 12)),
 							(0X6|(1<<6)),
@@ -545,9 +560,10 @@ ddr_set_t __ddr_setting = {
 
 #if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
 //lpddr3
-	.t_pub_zq0pr			= 0x0ca1c, //0x0ca1c,   //PUB ZQ0PR  //lpddr3
-	.t_pub_zq1pr			= 0x1cf3c,   //PUB ZQ1PR
-	.t_pub_zq2pr			= 0x1cf3c,   //PUB ZQ2PR
+	///**lpddr3 mcp
+	.t_pub_zq0pr			= 0x0ca58, //0x0ca1c,   //PUB ZQ0PR  //lpddr3
+	.t_pub_zq1pr			= 0x1cf39,   //PUB ZQ1PR  38 3b
+	.t_pub_zq2pr			= 0x1cf39,   //PUB ZQ2PR  38
 	.t_pub_zq3pr			= 0x1dd1d,   //PUB ZQ3PR
 
 /* 2layer board
@@ -607,8 +623,8 @@ ddr_set_t __ddr_setting = {
 ///*lpddr3
 #if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
 	.t_pub_acbdlr0			= 0,  //CK0 delay fine tune  TAKE CARE LPDDR3 ADD/CMD DELAY
-	.t_pub_aclcdlr			= 0,
-	.t_pub_acbdlr3			= 0x2020,//0,  //CK0 delay fine tune b-3f  //lpddr3 tianhe 2016-10-13
+	.t_pub_aclcdlr			= 0xf,
+	.t_pub_acbdlr3			= 0x0,//0,  //CK0 delay fine tune b-3f  //lpddr3 tianhe 2016-10-13
 #elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR4)
 //2layer board DDR4
 	.t_pub_acbdlr0			= 0, //0x3f,
@@ -629,20 +645,20 @@ ddr_set_t __ddr_setting = {
 #if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
 	//tianhe lpddr3 20161013
 	.wr_adj_per 			= {
-							[0] = 90, //aclcdlr
+							[0] = 100, //aclcdlr
 							[1] = 100,
-							[2] = 120,
-							[3] = 110,
-							[4] = 120,
-							[5] = 105,
+							[2] = 100,
+							[3] = 100,
+							[4] = 100,
+							[5] = 100,
 							},
 	.rd_adj_per				= {
 							[0] = 100,
 							[1] = 100,
-							[2] = 110,
-							[3] = 110,
-							[4] = 110,
-							[5] = 110,},
+							[2] = 100,
+							[3] = 100,
+							[4] = 100,
+							[5] = 100,},
 #else
 	/* P212 */
 	.wr_adj_per				= {