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错误记录 - [Synth 8-2543] port connections cannot be mixed ordered and named
错误记录 - [Synth 8-2543] port connections cannot be mixed ordered and named错误原因:最后一个端口括号后还有逗号(,)。ModuleTest ModuleTest_Test( .Port1 (Port1), .Port2 (Port2), .Port3 (Port3),);Port3...原创 2018-11-27 13:48:51 · 9428 阅读 · 1 评论 -
警告记录 - [Synth 8-3331] design has unconnected port
代码连接了端口但依然提示 design has unconnected port一个奇怪的警告,字面意思很清晰,有个端口未连接。顶层module Top( input wire wSysClk50M , input wire wRstKey_n , ... input wire wSDO //出问题 wire ); ... C...原创 2018-11-27 16:40:49 · 15133 阅读 · 0 评论 -
警告记录 - [Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance
[Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'ila_Top_inst' at clock pin 'clk' is different from the actual clock period '5.000', this can lead to differ...原创 2018-11-30 17:04:39 · 9749 阅读 · 8 评论