LLVM（四）：指令描述td部分

最新推荐文章于 2024-06-16 19:31:18 发布

windiwen

最新推荐文章于 2024-06-16 19:31:18 发布

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分类专栏： LLVM 文章标签： llvm 博客移植计划语言

本文链接：https://blog.csdn.net/huanglzg/article/details/20463441

版权

本文聚焦于LLVM中指令描述的TD部分，特别是针对ARM架构。内容涵盖指令属性，如编码、汇编输出、寄存器操作、匹配条件和DAG。通过实例说明了如何分类和描述ARM指令，如ADD、SUB等，并介绍了多类指令的实现方式。

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重要的指令属性

include/llvm/Target/Target.td中的instruction类是所有指令的父类。

//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
//
class Instruction {
  string Namespace = "";

  dag OutOperandList;       // An dag containing the MI def operand list.
  dag InOperandList;        // An dag containing the MI use operand list.
  string AsmString = "";    // The .s format to print the instruction with.

  // Pattern - Set to the DAG pattern for this instruction, if we know of one,
  // otherwise, uninitialized.
  list<dag> Pattern;

  // The follow state will eventually be inferred automatically from the
  // instruction pattern.

  list<Register> Uses = []; // Default to using no non-operand registers
  list<Register> Defs = []; // Default to modifying no non-operand registers

  // Predicates - List of predicates which will be turned into isel matching
  // code.
  list<Predicate> Predicates = [];

  // Size - Size of encoded instruction, or zero if the size cannot be determined
  // from the opcode.
  int Size = 0;

  // DecoderNamespace - The "namespace" in which this instruction exists, on
  // targets like ARM which multiple ISA namespaces exist.
  string DecoderNamespace = "";

  // Code size, for instruction selection.
  // FIXME: What does