BCLK = 2 * word_select_size * fs;
假如word_select_size = 32; fs = 44100;bclk=2.8224M;
bclk一般从一个master时钟分频下来,假如叫做mclk;
如果mclk由主控的pll或者其他时钟源提供,那么mclk由此pll分频或者倍频得到;
假如pll=22.5792M,需要得到bclk为2.8224M的频率;提供如下一组分频系数(也有可能是其它分频系数)供参考:
mclk = pll/4 = 5.6448M;bclk=mclk/2=2.8224M;
mdiv = 4;bdiv = 2;
over_samplerate = 5.6448M/44.1k = 128
mclk:有时为了使系统间能够更好地同步,还需要另外传输一个信号MCLK,称为主时钟,也叫系统时钟(Sys Clock),是采样频率的128倍,256倍或384倍,也叫过采样(over_samplerate);
lrck_period的配置:
pcm mode:number of bclks within(
left+right) channel width;
i2s/left-justified/right-justified mode:number of bclks within ech individual channel width(left or right)
N+1:
n=7; 8 bclk width
...
n=1023; 1024 bclks width;