FPGA调节LED亮度

2-1多周期-恒最大值计数-显示电路

手绘RLT图

生成的RLT图

源代码

包括用到的所有module：

module counterNdisplay(
		input clk,
		input rst,
		output wire [7:0] c_out );
		wire w1;
		wire [3:0] w2;
		divide_50000000_1 I_divide_50000000_1(.clk(clk),.rst(rst),.c_out(w1));
		counter_10 I_counter_10(.clk(w1),.rst(rst),.c_out(w2));
		four2eight I_four2eight(.c_in(w2),.rst(rst),.clk(w1),.c_out(c_out) );
endmodule


/**
*50Mhz to 1hz
*/
module divide_50000000_1(
		input clk,
		input rst,
		output reg c_out);
		integer k;
		always @(posedge rst,posedge clk)
		begin
			if(rst)
			begin
			k<=0;
			c_out<=0;
			end
			else
			begin
			if(k==25000000)
			begin
			c_out<=~c_out;
			k<=0;
			end
			else
			begin
			k<=k+1;
			end
			end
		end
endmodule
module counter_10(
		input clk,
		input rst,
		output reg [3:0] c_out);
		always @(posedge rst,posedge clk)
		begin
			if(rst)
			begin
				c_out<=4'b0000;
			end
			else
			begin 
				if(c_out==4'b1001)
			begin
				c_out<=4'b0000;
			end
			else
			begin
				c_out<=c_out+4'b0001;
			end
			end
		end
endmodule

/**
*4 bits number to 7-segment display
*/
module four2eight(
	input wire [3:0] c_in,
	input rst,
	input clk,
	output reg [7:0] c_out );
	always @(posedge rst,posedge clk) 
	begin
		if(rst)
		begin
			c_out<=8'b0100_0000;
		end
		else
		case(c_in)
			4'b0000:c_out<=8'b0100_0000;
			4'b0001:c_out<=8'b0111_1001;
			4'b0010:c_out<=8'b0010_0100;
			4'b0011:c_out<=8'b0011_0000;
			4'b0100:c_out<=8'b0001_1001;
			4'b0101:c_out<=8'b0001_0010;
			4'b0110:c_out<=8'b0000_0010;
			4'b0111:c_out<=8'b0111_1000;
			4'b1000:c_out<=8'b0000_0000;
			4'b1001:c_out<=8'b0001_0000;
		default:c_out<=8'b0100_0000;
		endcase
	end
endmodule