python处理sv接口文件，生成连接

python处理systemverilog接口文件，生成连接文件

文件1.sv

    wire [2:0] a;
    wire b;
    logic c;

读取文件1.sv，生成顶层连接文件init_top.sv

python脚本

import re

f = open('./1.sv','r')
sig = []
sig2 = []
for line in f.readlines():
    in_bru_r = re.search(r'\s*wire\s*\[\s*(\d+):(\d+)\]\s*(\w+)',line)
    if not (in_bru_r):
        in_bru_r_2 = re.search(r'\s*wire\s*(\w+)',line)
    if (not (in_bru_r)) and (not (in_bru_r_2)): 
        in_bru_r_3 = re.search(r'\s*logic\s*(\w+)',line)
    if (in_bru_r):
        #print(in_bru_r.group(3))
        sig.append(in_bru_r.group(3))
    elif (in_bru_r_2):
        #print(in_bru_r_2.group(1))
        sig.append(in_bru_r_2.group(1))
    else:
        #print(in_bru_r_3.group(1))
        sig.append(in_bru_r_3.group(1))

for i in range(len(sig)):
    #print(sig[i][2:])
    sig2.append(sig[i][2:])

f = open('top_init.sv','w')

st = []

for i in range(len(sig2)):
    a = "\tforce top_tb.U_DUT.u_dut_top." + str(sig2[i]) + " = " + 'm_' +str(sig2[i]) +";\n"
    st.append(a)

for i in range(len(st)):
    f.write(st[i])