VHDL

带请零端的8位并行输入串行输出移位寄存器(74166)
管脚定义:
a,b—h 8位并行输入信号
se 串行输入信号
q 串行输出信号
clk 时钟信号
fe 时钟信号禁止端
s1 移位装载控制端
reset 复位信号
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity ttl74166 is
port(reset,s1,fe,clk,se,a,b,c,d,e,f,g,h: in std_logic;
39
q: out std_logic);
end ttl74166;
architecture behave of ttl74166 is
signal tmpreg8: std_logic_vector(7 downto 0);
begin
process(clk,reset,s1,fe)
begin
if (reset='0') then --
tmpreg8<="00000000";
q<=tmpreg8(7);
elsif clk'event and clk='1' then
if (fe='0') then
if (s1='0') then
tmpreg8(0)<=a;
tmpreg8(1)<=b;
tmpreg8(2)<=c;
tmpreg8(3)<=d;
tmpreg8(4)<=e;
tmpreg8(5)<=f;
tmpreg8(6)<=g;
tmpreg8(7)<=h;
elsif (s1='1') then
for i in tmpreg8'high downto tmpreg8'low+1 loop
tmpreg8(i)<=tmpreg8(i-1);
end loop;
tmpreg8(tmpreg8'low)<=se;
q<=tmpreg8(7);
end if;
end if;
end if;
end process;
end behave;