verilog 笔记

repeat (1000) @(posedge clk);   //等待1000个时钟的上升沿

 

module dll_phaseshift(CLKIN, RESET, CLK0, CLK90, LOCKED);

 input CLKIN, RESET;

output CLK0, CLK90, LOCKED;

wire CLKIN_w, RESET_w, CLK0_dll, CLK90_dll, LOCKED_dll;

IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));

 IBUF rstpad (.I(RESET), .O(RESET_w));

CLKDLL dll (.CLKIN(CLKIN_w), .CLKFB(CLK0), .RST(RESET_w), .CLK0(CLK0_dll), .CLK90(CLK90_dll), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(), .LOCKED(LOCKED_dll));

BUFG clkg (.I(CLK0_dll), .O(CLK0));

 BUFG clk90g (.I(CLK90_dll), .O(CLK90));

OBUF lckpad (.I(LOCKED_dll), .O(LOCKED));

endmodule