//输入脉冲上升沿下降沿检测
reg wr_reg,wr_up,wr_down;
always@(posedge clk or negedge rst_n)
if(rst_n==1'b0) begin
wr_reg <= 1'b0;
wr_up <= 1'b0;
wr_down <= 1'b0;
end
else begin
wr_reg <= valid_wr;
wr_up <= valid_wr&(~wr_reg);
wr_down <= ~valid_wr&wr_reg;
end