USB设备的一些概念

每个USB设备有一个或多个配置来控制其行为;每个配置中都含有一个或多个接口;设备的接口具有一个或多个端点,每个USB设备在主机看来就是一些端点的结合,提取一个端点的地址、缓冲区长度、数据传输方向、类别等信息,就把一个端点封装成一个管道,利用这个管道句柄就可以实现主机与一个内存缓冲区和设备多个端点之间的数据传输。

 

USB通信模型,它表明了端点和管道所扮演的角色。整个模型分为3级结构:在最低一级,USB电缆把主控制器与设备的总线接口连接起来;在第二级,一个控制管道把系统软件与逻辑设备连接起来;在第三级,一捆数据管道把客户软件与一组接口连接起来,这些接口组成设备的功能.

 

Descriptor是描述符,并存储在USB设备中,用于描述一个USB设备的所有属性,USB主机是通过一系列命令(URB)要求设备发送这些信息. 描述附共有如下:

1——设备描述符

2——配置描述符

           struct _CONFIGURATION_DEscriptOR_STRUCT

{

 BYTE bLength;          //描述符的长度

 BYTE bDescriptorType;  //描述符类型编号

 WORD wTotalLength;     //配置所返回的所有数量的大小

 BYTE bNumInterface;    //此配置所支持的接口数量

 BYTE bConfigurationVale;   //Set_Configuration命令需要的参数值

 BYTE iConfiguration;       //描述该配置的字符串的索引值

 BYTE bmAttribute;          //供电模式的选择

 BYTE MaxPower;             //设备从总线提取的最大电流

}

 

3——字符描述符

4——接口描述符

      struct _INTERFACE_DESCRIPTOR_STRUCT

{

 BYTE bLength;          //长度

 BYTE bDescriptorType;  //描述符类型编号

 BYTE bInterfaceNunber; //接口的编号

 BYTE bAlternateSetting;//备用的接口描述符编号

 BYTE bNumEndpoints;    //该接口使用端点数,不包括端点0

 BYTE bInterfaceClass;  //接口类型

 BYTE bInterfaceSubClass;//接口子类型

 BYTE bInterfaceProtocol;//接口所遵循的协议

 BYTE iInterface;        //描述该接口的字符串索引值

}

 

5——端点描述符;

       struct _ENDPOIN_DESCRIPTOR_STRUCT

{

 BYTE bLength;          //长度

 BYTE bDescriptorType;  //描述符类型编号

 BYTE bEndpointAddress; //端点地址

 BYTE bmAttribute;      //端点的传输类型属性

 WORD wMaxPacketSize;   //端点收、发的最大包的大小

 BYTE bInterval;        //主机查询端点的时间间隔

}

描述符之间的关系,一个设备只有一个设备描述符,而一个设备描述符可以包含多个配置描述符,而一个配置描述符可以包含多个接口描述符,一个接口使用了几个端点,就有几个端点描述符。

 

 

 

WDM驱动程序模型中的每个硬件设备都有两个驱动:功能驱动和总线驱动。功能驱动了解使硬件工作的所有细节,负责初始化I/O操作,处理I/O操作完成时所带来的中断事件,为用户提供一种设备适合的控制方式; 总线驱动程序(USB DriverUSBD)负责管理硬件与计算机的连接,实现繁琐的底层通信。总线驱动包括主控制器驱动程序(OPENHCI.SYS或者UHCD.SYS)hub驱动程序(USBHUB.SYS),一个由控制器驱动程序使用的类驱动程序(USBD.SYS)和发现USB主控制器并会装入相关功能驱动程序。

 

USB设备驱动程序通过发送URBUSB Request Block)和IRPI/O Request Packet)来使用总线驱动并完成对物理硬件的操作。设备驱动会创建一个URB并提交到总线驱动程序USBD.SYS,这样,向USBD的调用被转化为带有主功能代码为IRP_MJ_INTERNAL_DEVICE_CONTROLIRP。然后USBD再调度总线时间,发出URB中指定的操作,完成收发数据包请求。

 

USB 驱动程序是绑定到USB 接口上,而不是绑定到整个USB设备上。

 

驱动程序对象与设备对象的关系:
一方面, 驱动程序对象通常有多个与它相关的设备对象,因此它利用DeviceObject指针指向一个设备对象列表,该列表表示驱动程序可以控制的物理设备;
另一方面, 设备对象反过来指向它自己的驱动程序对象, 这样I/O管理器就知道在接收一个I/O请求时应该调用哪个驱动程序。每个功能码都对应一个驱动程序的入口点.

 
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TABLE OF CONTENTS<br>1. INTRODUCTION.........................................................................................................1<br>2. TERMS AND ABBREVIATIONS.................................................................................2<br>3. ARCHITECTURAL OVERVIEW..................................................................................6<br>3.1 Introduction..........................................................................................................6<br>3.2 Data Transfer Types............................................................................................7<br>3.3 Host Controller Interface.....................................................................................7<br>3.3.1 Communication Channels............................................................................................7<br>3.3.2 Data Structures...........................................................................................................8<br>3.4 Host Controller Driver Responsibilities...........................................................12<br>3.4.1 Host Controller Management....................................................................................12<br>3.4.2 Bandwidth Allocation................................................................................................12<br>3.4.3 List Management......................................................................................................13<br>3.4.4 Root Hub..................................................................................................................13<br>3.5 Host Controller Responsibilities......................................................................13<br>3.5.1 USB States...............................................................................................................13<br>3.5.2 Frame management...................................................................................................14<br>3.5.3 List Processing..........................................................................................................14<br>4. DATA STRUCTURES...............................................................................................15<br>4.1 Overview.............................................................................................................15<br>4.2 Endpoint Descriptor..........................................................................................16<br>4.2.1 Endpoint Descriptor Format......................................................................................16<br>4.2.2 Endpoint Descriptor Field Definitions........................................................................17<br>4.2.3 Endpoint Descriptor Description...............................................................................18<br>4.3 Transfer Descriptors.........................................................................................19<br>4.3.1 General Transfer Descriptor......................................................................................19<br>4.3.1.1 General Transfer Descriptor Format...................................................................20<br>4.3.1.2 General Transfer Descriptor Field Definitions.....................................................20<br>4.3.1.3 General Transfer Descriptor Description.............................................................21<br>4.3.1.3.1 Buffer Address Determination.....................................................................21<br>4.3.1.3.2 Packet Size..................................................................................................21<br>4.3.1.3.3 Condition Codes..........................................................................................22<br>4.3.1.3.4 Sequence Bits..............................................................................................22<br>4.3.1.3.5 Transfer Completion....................................................................................23<br>4.3.1.3.6 Transfer Errors............................................................................................23<br>4.3.1.3.6.1 Transmission Errors..............................................................................24<br>4.3.1.3.6.2 Sequence Errors...................................................................................24<br>vi<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>4.3.1.3.6.3 System Errors.......................................................................................25<br>4.3.1.3.7 Special Handling..........................................................................................25<br>4.3.1.3.7.1 NAK.....................................................................................................25<br>4.3.1.3.7.2 Stall......................................................................................................25<br>4.3.2 Isochronous Transfer Descriptor...............................................................................25<br>4.3.2.1 Isochronous Transfer Descriptor Format............................................................25<br>4.3.2.2 Isochronous Transfer Descriptor Field Definitions..............................................26<br>4.3.2.3 Isochronous Transfer Descriptor Description......................................................26<br>4.3.2.3.1 Buffer Addressing........................................................................................27<br>4.3.2.3.2 Data Packet Size.........................................................................................28<br>4.3.2.3.3 Status..........................................................................................................28<br>4.3.2.3.4 Transfer Completion....................................................................................28<br>4.3.2.3.5 Transfer Errors............................................................................................28<br>4.3.2.3.5.1 Transmission Errors..............................................................................29<br>4.3.2.3.5.2 Sequence Errors...................................................................................29<br>4.3.2.3.5.3 Time Errors..........................................................................................29<br>4.3.2.3.5.4 System Errors.......................................................................................30<br>4.3.2.3.6 Special Handling..........................................................................................31<br>4.3.2.3.6.1 NAK and STALL.................................................................................31<br>4.3.2.4 PacketStatusWord..............................................................................................31<br>4.3.2.4.1 Packet Status Word Field Definitions...........................................................31<br>4.3.3 Completion Codes.....................................................................................................32<br>4.3.3.1 Condition Code Description...............................................................................33<br>4.4 Host Controller Communications Area............................................................33<br>4.4.1 Host Controller Communications Area Format..........................................................34<br>4.4.2 Host Controller Communications Area Description...................................................34<br>4.4.2.1 HccaInterruptTable............................................................................................34<br>4.4.2.2 HccaFrameNumber............................................................................................35<br>4.4.2.3 HccaDoneHead..................................................................................................35<br>4.5 Endpoint List Processing.................................................................................36<br>4.6 Transfer Descriptor Queue Processing...........................................................37<br>5. HOST CONTROLLER DRIVER................................................................................38<br>5.1 Host Controller Management............................................................................38<br>5.1.1 Initialization..............................................................................................................38<br>5.1.1.1 Load and Locate................................................................................................39<br>5.1.1.2 Verify Host Controller and Allocate Resources...................................................39<br>5.1.1.3 Take Control of Host Controller.........................................................................40<br>5.1.1.3.1 SMM Driver, Power-Up..............................................................................40<br>5.1.1.3.2 BIOS Driver................................................................................................40<br>5.1.1.3.3 OS Driver, SMM Active..............................................................................41<br>5.1.1.3.4 OS Driver, BIOS Active..............................................................................41<br>5.1.1.3.5 OS Driver, neither SMM nor BIOS.............................................................41<br>5.1.1.3.6 SMM Driver, Re-Entry................................................................................42<br>vii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>5.1.1.4 Setup Host Controller........................................................................................42<br>5.1.1.5 Begin Sending SOFs...........................................................................................42<br>5.1.2 Operational States.....................................................................................................43<br>5.1.2.1 USBRESET..........................................................................................................43<br>5.1.2.2 USBOPERATIONAL..............................................................................................43<br>5.1.2.3 USBSUSPEND......................................................................................................43<br>5.1.2.4 USBRESUME.......................................................................................................44<br>5.2 Schedule.............................................................................................................44<br>5.2.1 Sample Host Controller Driver Definitions................................................................46<br>5.2.2 Miscellaneous Definitions..........................................................................................46<br>5.2.3 Host Controller Descriptors Definitions.....................................................................47<br>5.2.4 Host Controller Driver Descriptor Definitions...........................................................48<br>5.2.5 Host Controller Endpoints........................................................................................50<br>5.2.6 Host Controller Driver Internal Definitions................................................................51<br>5.2.7 Endpoint Descriptor Lists.........................................................................................54<br>5.2.7.1 Bulk and Control................................................................................................54<br>5.2.7.1.1 Adding........................................................................................................54<br>5.2.7.1.2 Removing....................................................................................................56<br>5.2.7.1.3 Pause...........................................................................................................59<br>5.2.7.2 Interrupt.............................................................................................................61<br>5.2.7.2.1 Polling Rate.................................................................................................64<br>5.2.7.2.2 Adding........................................................................................................66<br>5.2.7.2.3 Removing....................................................................................................66<br>5.2.7.2.4 Pause...........................................................................................................67<br>5.2.7.3 Isochronous.......................................................................................................67<br>5.2.7.3.1 Adding........................................................................................................68<br>5.2.7.3.2 Removing....................................................................................................68<br>5.2.7.3.3 Pause...........................................................................................................68<br>5.2.8 Transfer Descriptor Queues......................................................................................68<br>5.2.8.1 The NULL or Empty Queue...............................................................................68<br>5.2.8.2 Adding to a Queue.............................................................................................69<br>5.2.8.3 Removing from a Queue.....................................................................................73<br>5.2.8.4 Cancel................................................................................................................74<br>5.2.9 Done Queue..............................................................................................................75<br>5.2.10 USB Bandwidth Allocation.....................................................................................78<br>5.2.10.1 Scheduling Overrun Errors...............................................................................78<br>5.2.11 ControlBulkServiceRatio........................................................................................79<br>5.3 Host Controller Interrupt...................................................................................80<br>5.4 FrameInterval Counter.......................................................................................85<br>5.5 Root Hub............................................................................................................86<br>viii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6. HOST CONTROLLER..............................................................................................87<br>6.1 Introduction........................................................................................................87<br>6.2 USB States.........................................................................................................87<br>6.2.1 UsbOperational.........................................................................................................88<br>6.2.2 UsbReset..................................................................................................................89<br>6.2.3 UsbSuspend..............................................................................................................89<br>6.2.4 UsbResume...............................................................................................................89<br>6.3 Frame Management...........................................................................................90<br>6.3.1 Frame Timing............................................................................................................90<br>6.3.2 StartOfFrame (SOF) Token Generation.....................................................................91<br>6.3.3 HccaFrameNumber Update.......................................................................................91<br>6.4 List Processing..................................................................................................92<br>6.4.1 Priority.....................................................................................................................92<br>6.4.1.1 List Priority........................................................................................................93<br>6.4.1.1.1 Periodic Lists...............................................................................................93<br>6.4.1.1.2 Nonperiodic Lists........................................................................................93<br>6.4.1.2 Endpoint Descriptor Priority..............................................................................94<br>6.4.1.3 Transfer Descriptor Priority................................................................................95<br>6.4.2 List Service Flow......................................................................................................95<br>6.4.2.1 List Enabled Check............................................................................................95<br>6.4.2.2 Locating Endpoint Descriptors...........................................................................97<br>6.4.3 Endpoint Descriptor Processing................................................................................98<br>6.4.4 Transfer Descriptor Processing.................................................................................99<br>6.4.4.1 Isochronous Relative Frame Number Calculation................................................99<br>6.4.4.2 Packet Address and Size Calculation..................................................................99<br>6.4.4.3 Packet Transfer Time Check.............................................................................101<br>6.4.4.4 Largest Data Packet Counter Operation...........................................................102<br>6.4.4.5 Status Writeback..............................................................................................102<br>6.4.4.5.1 General Transfer Descriptor Status Writeback...........................................102<br>6.4.4.5.2 Isochronous Transfer Descriptor Status Writeback....................................103<br>6.4.4.6 Transfer Descriptor Retirement........................................................................103<br>6.4.5 Done Queue............................................................................................................104<br>6.4.5.1 Done Queue Interrupt Counter.........................................................................104<br>6.5 Interrupt Processing........................................................................................105<br>6.5.1 SchedulingOverrun Event........................................................................................105<br>6.5.2 WritebackDoneHead Event.....................................................................................106<br>6.5.3 StartOfFrame Event................................................................................................106<br>6.5.4 ResumeDetected Event...........................................................................................106<br>6.5.5 UnrecoverableError Event......................................................................................106<br>6.5.6 FrameNumberOverflow Event.................................................................................106<br>6.5.7 RootHubStatusChange Event..................................................................................107<br>6.5.8 OwnershipChange Event.........................................................................................107<br>ix<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6.6 Root Hub..........................................................................................................107<br>7. OPERATIONAL REGISTERS.................................................................................108<br>7.1 The Control and Status Partition....................................................................109<br>7.1.1 HcRevision Register................................................................................................109<br>7.1.2 HcControl Register.................................................................................................109<br>7.1.3 HcCommandStatus Register....................................................................................112<br>7.1.4 HcInterruptStatus Register......................................................................................113<br>7.1.5 HcInterruptEnable Register....................................................................................115<br>7.1.6 HcInterruptDisable Register...................................................................................116<br>7.2 Memory Pointer Partition................................................................................117<br>7.2.1 HcHCCA Register...................................................................................................117<br>7.2.2 HcPeriodCurrentED Register.................................................................................117<br>7.2.3 HcControlHeadED Register...................................................................................118<br>7.2.4 HcControlCurrentED Register................................................................................118<br>7.2.5 HcBulkHeadED Register........................................................................................119<br>7.2.6 HcBulkCurrentED Register.....................................................................................119<br>7.2.7 HcDoneHead Register............................................................................................120<br>7.3 Frame Counter Partition..................................................................................120<br>7.3.1 HcFmInterval Register............................................................................................120<br>7.3.2 HcFmRemaining Register.......................................................................................121<br>7.3.3 HcFmNumber Register...........................................................................................122<br>7.3.4 HcPeriodicStart Register........................................................................................122<br>7.3.5 HcLSThreshold Register.........................................................................................123<br>7.4 Root Hub Partition...........................................................................................123<br>7.4.1 HcRhDescriptorA Register......................................................................................124<br>7.4.2 HcRhDescriptorB Register......................................................................................125<br>7.4.3 HcRhStatus Register...............................................................................................126<br>7.4.4 HcRhPortStatus[1:NDP] Register...........................................................................128<br>APPENDIX A—PCI INTERFACE................................................................................132<br>PCI CONFIGURATION...............................................................................................132<br>PCI Configuration Spaces for OpenHCI-compliant USB Host Controller.........133<br>COMMAND Register.......................................................................................................134<br>CLASS_CODE Register...................................................................................................134<br>BAR_OHCI Register........................................................................................................135<br>x<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>APPENDIX B—LEGACY SUPPORT INTERFACE SPECIFICATION........................136<br>OVERVIEW.................................................................................................................136<br>OPERATIONAL THEORY..........................................................................................137<br>Keyboard/Mouse Input..........................................................................................137<br>Keyboard Output...................................................................................................138<br>Emulation Interrupts..............................................................................................138<br>Mixed Environment.........................................................................................................139<br>Gate A20 Sequence.........................................................................................................139<br>SYSTEM REQUIREMENTS........................................................................................140<br>Host Controller Mapping.......................................................................................140<br>SMI Signaling.........................................................................................................141<br>Intercept Port 60h and 64h Accesses..................................................................141<br>Interrupts................................................................................................................141<br>Run-time Memory ..................................................................................................141<br>PROGRAMMING INTERFACE...................................................................................142<br>Modifications to existing registers......................................................................142<br>HcRevision Register........................................................................................................142<br>Legacy Support Registers....................................................................................142<br>HceInput Register............................................................................................................143<br>HceOutput Register.........................................................................................................143<br>HceStatus Register...........................................................................................................144<br>HceControl Register........................................................................................................145<br>IMPLEMENTATION NOTES.......................................................................................146<br>Emulation Interrupt Decode..................................................................................146<br>A20 Gate.................................................................................................................146
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