/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Gary Jennejohn <gj@denx.de>
* David Mueller <d.mueller@elsoft.ch>
*
* Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
这里粗粗解释了配置文件，可能有很多错，还望各位前辈指出。
*/
#ifndef __CONFIG_H//config.h中定义了forlinx_boot_nand和forlinx_boot_ram256
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_S3C6410 1 /* in a SAMSUNG S3C6410 SoC */
#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
#define CONFIG_SMDK6410 1 /* on a SAMSUNG SMDK6410 Board */
//#define CONFIG_SMDK6410_X5A 1 /* on a SAMSUNG SMDK6410 OneNAND POP Board 不使用onenand*/
#define MEMORY_BASE_ADDRESS 0x50000000
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* the SMDK6400 has 12MHz input clock */
#ifdef FORLINX_BOOT_NAND
#define CONFIG_ENABLE_MMU
#endif
#ifdef CONFIG_ENABLE_MMU
#define virt_to_phys(x) virt_to_phy_smdk6410(x)
#else
#define virt_to_phys(x) (x)
#endif
#define CONFIG_MEMORY_UPPER_CODE//堆栈初始化代码
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff不使用中断和快速中断 */
#define CONFIG_INCLUDE_TEST
#define CONFIG_ZIMAGE_BOOT?/引导内核命令
#define CONFIG_IMAGE_BOOT?/同上
#define BOARD_LATE_INIT?/延时操作
#define CONFIG_SETUP_MEMORY_TAGS?/ram信息标签，用于向内核传递uboot参数
#define CONFIG_CMDLINE_TAG?/同上 命令行标签
#define CONFIG_INITRD_TAG//同上 初始ram磁盘标签
/*
* Architecture magic and machine type
*/
#define MACH_TYPE 1626
#define UBOOT_MAGIC (0x43090000 | MACH_TYPE)
/* Power Management is enabled 电源管理*/
#define CONFIG_PM
#define CONFIG_DISPLAY_CPUINFO?/显示cpu型号
#define CONFIG_DISPLAY_BOARDINFO//显示板号
#undef CONFIG_SKIP_RELOCATE_UBOOT//不实用重定位
#undef CONFIG_USE_NOR_BOOT//不实用onenand
/*
* Size of malloc() pool申请的内存大小
*/
//#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data 初始数据大小*/
#define CFG_STACK_SIZE 512*1024?/堆栈大小
/*
* Hardware drivers无此外设
*/
//#define CONFIG_DRIVER_SMC911X 1 /* we have a SMC9115 on-board */
#ifdef CONFIG_DRIVER_SMC911X
#undef CONFIG_DRIVER_CS8900
#define CONFIG_DRIVER_SMC911X_BASE 0x18800300
#else
#define CONFIG_DRIVER_CS8900 0 /* we have a CS8900 on-board */
#define CS8900_BASE 0x18800300
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
#endif
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
#define CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CONFIG_CMDLINE_EDITING
//#undef CONFIG_S3C64XX_I2C /* this board has H/W I2C */
#define CONFIG_S3C64XX_I2C /*add by phantom*/
#ifdef CONFIG_S3C64XX_I2C
#define CONFIG_HARD_I2C 1
#define CFG_I2C_SPEED 10000?/I2C时钟SCL
#define CFG_I2C_SLAVE 0xFE?/I2C从属设备号
#endif
#define CONFIG_DOS_PARTITION//关于分区
#define CONFIG_SUPPORT_VFAT?
#define CONFIG_USB_OHCI
#undef CONFIG_USB_STORAGE
#define CONFIG_S3C_USBD
#define USBD_DOWN_ADDR 0xc0000000//usb下载地址dnw
/************************************************************
* RTC实时时钟
************************************************************/
#define CONFIG_RTC_S3C64XX 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_CACHE | \
CFG_CMD_USB | \
CFG_CMD_REGINFO | \
CFG_CMD_LOADS | \
CFG_CMD_LOADB | \
CFG_CMD_ENV | \
CFG_CMD_NAND | \
CFG_CMD_MOVINAND| \
CFG_CMD_ONENAND | \
CFG_CMD_DATE | \
CFG_CMD_PING | \
CFG_CMD_FAT | \
CFG_CMD_ELF) \
& ~(CFG_CMD_AUTOSCRIPT | \
CFG_CMD_BOOTD | \
CFG_CMD_IMI | \
CFG_CMD_RUN | \
CFG_CMD_CONSOLE | \
CFG_CMD_DOCG3P3 | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
0)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=yaffs2 console=ttySAC0,115200"
#define CONFIG_ETHADDR 00:40:5c:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.1.20
#define CONFIG_SERVERIP 192.168.1.10
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_ZERO_BOOTDELAY_CHECK
/*#define CONFIG_NET_MULTI 1 */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "SMDK6410 # " /* Monitor Command Prompt 命令提示符*/
#define CFG_CBSIZE 256 /* Console I/O Buffer Size控制台IO缓冲区大小 */
#define CFG_PBSIZE 384 /* Print Buffer Size打印缓冲大小 */
#define CFG_MAXARGS 16 /* max number of command args 最大命令变量数16条*/
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size 板子参数大小*/
#define CFG_MEMTEST_START MEMORY_BASE_ADDRESS /* memtest works on内存检测开始地址 */
#define CFG_MEMTEST_END MEMORY_BASE_ADDRESS + 0x7e00000 /* 128 MB in DRAM 结束地址*/
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR MEMORY_BASE_ADDRESS /* default load address */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define CFG_HZ 1562500 // at PCLK 50MHz像素始时钟
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack 中断*/
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack 异常中断*/
#endif
//#define CONFIG_CLK_800_133_66
//#define CONFIG_CLK_666_133_66
#define CONFIG_CLK_532_133_66
//#define CONFIG_CLK_400_133_66
//#define CONFIG_CLK_400_100_50
//#define CONFIG_CLK_OTHERS
#define CONFIG_CLKSRC_CLKUART
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
#if defined(CONFIG_CLK_666_133_66) /* FIN 12MHz, Fout 666MHz */
#define APLL_MDIV 333
#define APLL_PDIV 3
#define APLL_SDIV 1
#undef CONFIG_SYNC_MODE /* ASYNC MODE */
#elif defined(CONFIG_CLK_532_133_66) /* FIN 12MHz, Fout 532MHz */
#define APLL_MDIV 266
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_400_133_66) || defined(CONFIG_CLK_800_133_66) /* FIN 12MHz, Fout 800MHz */
#define APLL_MDIV 400
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_400_100_50) /* FIN 12MHz, Fout 400MHz */
#define APLL_MDIV 400
#define APLL_PDIV 3
#define APLL_SDIV 2
#define CONFIG_SYNC_MODE
#elif defined(CONFIG_CLK_OTHERS)
/*If you have to use another value, please define pll value here*/
/* FIN 12MHz, Fout 532MHz */
#define APLL_MDIV 266
#define APLL_PDIV 3
#define APLL_SDIV 1
#define CONFIG_SYNC_MODE
#else
#error "Not Support Fequency or Mode!! you have to setup right configuration."
#endif
#define CONFIG_UART_66 /* default clock value of CLK_UART */
#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
/* prevent overflow */
#define Startup_APLL (CONFIG_SYS_CLK_FREQ/(APLL_PDIV<<APLL_SDIV)*APLL_MDIV)
/* fixed MPLL 533MHz */
#define MPLL_MDIV 266
#define MPLL_PDIV 3
#define MPLL_SDIV 1
#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
/* prevent overflow */
#define Startup_MPLL ((CONFIG_SYS_CLK_FREQ)/(MPLL_PDIV<<MPLL_SDIV)*MPLL_MDIV)
#if defined(CONFIG_CLK_800_133_66)
#define Startup_APLLdiv 0
#define Startup_HCLKx2div 2
#elif defined(CONFIG_CLK_400_133_66)
#define Startup_APLLdiv 1
#define Startup_HCLKx2div 2
#else
#define Startup_APLLdiv 0
#define Startup_HCLKx2div 1
#endif
#define Startup_PCLKdiv 3
#define Startup_HCLKdiv 1
#define Startup_MPLLdiv 1
#define CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
#if defined(CONFIG_SYNC_MODE)
#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
#else
#define Startup_HCLK (Startup_MPLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map物理内存映射
*/
#ifndef CONFIG_SMDK6410_X5A
// 128 MB SDRAM
#if defined(FORLINX_BOOT_RAM128)
#define DMC1_MEM_CFG 0x00010012 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
#define DMC1_CHIP0_CFG 0x150F8
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
//256 MB SDRAM
#elif defined(FORLINX_BOOT_RAM256)
#define DMC1_MEM_CFG 0x0001001a /* Supports one CKE control, Chip1, Burst4, Row/Column bit 存储配置寄存器*/
#define DMC1_CHIP0_CFG 0x150F0
#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
#else
#error RAM size must be defined
#endif
#define DMC1_MEM_CFG2 0xB45?/存储配置寄存器2 详见芯片手册
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters内存参数 */
/* DDR Parameters */
#define DDR_tREFRESH 7800 /* ns */
#define DDR_tRAS 45 /* ns (min: 45ns)*/
#define DDR_tRC 68 /* ns (min: 67.5ns)*/
#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
#define DDR_tRFC 80 /* ns (min: 80ns)*/
#define DDR_tRP 23 /* ns (min: 22.5ns)*/
#define DDR_tRRD 15 /* ns (min: 15ns)*/
#define DDR_tWR 15 /* ns (min: 15ns)*/
#define DDR_tXSR 120 /* ns (min: 120ns)*/
#define DDR_CASL 3 /* CAS Latency 3 */
#else
#define DMC1_MEM_CFG 0x00210011 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
#define DMC1_MEM_CFG2 0xB41
#define DMC1_CHIP0_CFG 0x150FC
#define DMC1_CHIP1_CFG 0x154FC
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
/* DDR Parameters */
#define DDR_tREFRESH 5865 /* ns */
#define DDR_tRAS 50 /* ns (min: 45ns)*/
#define DDR_tRC 68 /* ns (min: 67.5ns)*/
#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
#define DDR_tRFC 133 /* ns (min: 80ns)*/
#define DDR_tRP 23 /* ns (min: 22.5ns)*/
#define DDR_tRRD 20 /* ns (min: 15ns)*/
#define DDR_tWR 20 /* ns (min: 15ns)*/
#define DDR_tXSR 125 /* ns (min: 120ns)*/
#define DDR_CASL 3 /* CAS Latency 3 */
#endif
/*
* mDDR memory configuration
*/
#define DMC_DDR_BA_EMRS 2
#define DMC_DDR_MEM_CASLAT 3
#define DMC_DDR_CAS_LATENCY (DDR_CASL<<1) //6 Set Cas Latency to 3
#define DMC_DDR_t_DQSS 1 // Min 0.75 ~ 1.25
#define DMC_DDR_t_MRD 2 //Min 2 tck
#define DMC_DDR_t_RAS (((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1) //7, Min 45ns
#define DMC_DDR_t_RC (((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1) //10, Min 67.5ns
#define DMC_DDR_t_RCD (((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1) //4,5(TRM), Min 22.5ns
#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
#define DMC_DDR_t_RFC (((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1) //11,18(TRM) Min 80ns
#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
#define DMC_DDR_t_RP (((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1) //4, 5(TRM) Min 22.5ns
#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
#define DMC_DDR_t_RRD (((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1) //3, Min 15ns
#define DMC_DDR_t_WR (((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1) //Min 15ns
#define DMC_DDR_t_WTR 2
#define DMC_DDR_t_XP 2 //1tck + tIS(1.5ns)
#define DMC_DDR_t_XSR (((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1) //17, Min 120ns
#define DMC_DDR_t_ESR DMC_DDR_t_XSR
#define DMC_DDR_REFRESH_PRD (((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000) // TRM 2656
#define DMC_DDR_USER_CONFIG 1 // 2b01 : mDDR
#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 bank of DRAM */
#define PHYS_SDRAM_1 MEMORY_BASE_ADDRESS /* SDRAM Bank #1 */
#define CFG_FLASH_BASE 0x00000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 0 /* max number of memory banks 内存条数*/
#define CFG_MAX_FLASH_SECT 1024?/flash分割最大块数
#define CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE 0x100000//一兆
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase 5*50hz */
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_ADDR 0
//#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*
* SMDK6400 board specific data
*/
#define CONFIG_IDENT_STRING " for SMDK6410"
/* total memory required by uboot */
#define CFG_UBOOT_SIZE (2*1024*1024)//uboot被分配的总大小2m
/* base address for uboot 基地址*/
#ifdef CONFIG_ENABLE_MMU
#define CFG_UBOOT_BASE TEXT_BASE//大小为CFE0 0000
#define CFG_PHY_UBOOT_BASE (MEMORY_BASE_ADDRESS + (TEXT_BASE - 0xC0000000))//重新映射uboot物理地址=?使用动态存储区dmc1地址5000 0000 -6fff ffff，至于这个c000 0000我也不太清楚
#else
#define CFG_UBOOT_BASE TEXT_BASE
#define CFG_PHY_UBOOT_BASE TEXT_BASE
#endif
//#define CFG_ENV_OFFSET 0x0003c000
//#define CFG_ENV_OFFSET 0x00080000
/* NAND configuration */
#define CFG_MAX_NAND_DEVICE 1
#define CFG_NAND_BASE (0x70200010)//详见芯片手册内存映射章节，7000 0000 -7fff ffff地址用于外设
#define NAND_MAX_CHIPS 1//nand条数
#define NAND_DISABLE_CE() (NFCONT_REG |= (1 << 1))
#define NAND_ENABLE_CE() (NFCONT_REG &= ~(1 << 1))
#define NF_TRANSRnB() do { while(!(NFSTAT_REG & (1 << 0))); } while(0)
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_WP 1
#define CFG_NAND_YAFFS_WRITE 1 /* support yaffs write */
//#define CFG_NAND_4K_SIZE
//#define CFG_NAND_8K_SIZE
/* Boot configuration (define only one of next) */
/*
* BL1 should be written in the block0 with 8 bit ecc parity codes注意这段英文
* Enable this definition if you use iROM-NAND boot
*/
#define CONFIG_NAND_BL1_8BIT_ECC
/* Settings as above boot configuration */
#define CONFIG_NAND
#define CONFIG_MOVINAND
#define CFG_NAND_HWECC?/启用硬件ecc
#if defined(FORLINX_BOOT_NAND)
#define CONFIG_BOOT_NAND
#define CFG_ENV_IS_IN_NAND//环境变量存储在nand中
//#define CFG_NAND_LARGEPAGE_SAVEENV
//#define CFG_NAND_FLASH_BBT
#define CONFIG_BOOTCOMMAND "nand read 0xc0008000 0x100000 0x500000;bootm 0xc0008000"//读取内核映像c0008000是什么含义?下载地址?
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 512*1024)//环境变量大小512kb
#define CFG_ENV_SIZE 0x80000 /* Total Size of Environment Sector 8M 环境变量所在扇区大小*/
#define CFG_ENV_OFFSET 0x00080000//偏移量
#elif defined(FORLINX_BOOT_SD)//SD卡启动
#define FORLINX_DEBUG
#define CONFIG_MMC 1
#define CONFIG_LCD
#define CONFIG_BOOT_MOVINAND
#define CFG_ENV_IS_IN_MOVINAND
#define CONFIG_BOOTCOMMAND "nand erase;fatload mmc 0:1 0x50008000 u-boot.bin;nand write.uboot 0x50008000 0 0x100000;fatload mmc 0:1 0x50008000 zImage;nand write.e 0x50008000 0x100000 0x500000; fatload mmc 0:1 0x50008000 rootfs.yaffs2; nand write.yaffs2 0x50008000 0x00600000 $filesize; nand ok "
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 1024*1024)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#define CFG_ENV_OFFSET 0x0003c000
#elif defined(CONFIG_BOOT_ONENAND) || defined(CONFIG_BOOT_ONENAND_IROM)
#define CFG_ONENAND_BASE (0x70100000)
#define CFG_MAX_ONENAND_DEVICE 1
#define CFG_ENV_IS_IN_ONENAND
#define CONFIG_BOOTCOMMAND "onenand read c0008000 40000 3c0000;bootm c0008000"
#else
# error Define one of CONFIG_BOOT_{NAND|MOVINAND|ONENAND|ONENAND_IROM}
#endif
#endif /* __CONFIG_H */
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