MC9S08GT60(1)

Analog-to-Digital Converter (ATD) Module

 

 

 

ATD Control (ATDC)

对ATD control register写入，会中断当前的转换，但是会启动一个新转换。

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	ATDPU	DJM	RES8	SGN	PRS
写
复位	0	0	0	0	0	0	0	0

 

 

 

ATDPU — ATD Power Up

用来在不需要ADT的时候，降低对电源的消耗，清零时，会终止当前的转换。

1 = ATD functionality.

0 = Disable the ATD and enter a low-power state.

 

 

 

DJM — Data Justification Mode

用来确定转换的10位数据和ATD result register bits的对应关系。当RES8被置1，DJM就是无效位8位数据直接放在ATD1RH

对于left-justified mode转换结果的9－2位对应ATD1RH的7－0，转换结果的1和0位对应ATD1RL的7和6位，ATD1RH的第7位是MSB

 

 

 

 

 

 

对于right-justified mode转换结果的9和8位对应ATD1RH的1和0位，转换结果的7－0位对应ATD1RL的7－0，，ATD1RH的第1位是MSB

 

 

 

 

 

 

1 = Result register data is right justified.

0 = Result register data is left justified.

 

 

 

RES8 — ATD Resolution Select

1 = 8-bit resolution selected.

0 = 10-bit resolution selected.

 

 

 

SGN — Signed Result Select

用来确定数据是否为有符数据，有符数据模式只能在left justified (DJM = 0)时用，对于right-justified mode(DJM = 1)则不适用。当选择的是有符模式，转换的结果的范围就变为–512 ($200) ——511($1FF) 对于 10-bit resolution 和–128 ($80) ——127 ($7F) 对于 8-bit resolution.

 

 

 

1 = Left justified result data is signed.

0 = Left justified result data is unsigned.

RES8	DJM	SGN	Data Formats of Result	Analog Input VREFH = VDDA, VREFL = VSSA ATD1RH:ATD1RL
				VDDA	VSSA
1	0	0	8-bit : left justified : unsigned	$FF:$00	$00:$00
1	0	1	8-bit : left justified : signed	$7F:$00	$80:$00
1	1	X1	8-bit : right justified2: unsigned	$FF:$00	$00:$00
0	0	0	10-bit : left justified : unsigned	$FF:$C0	$00:$00
0	0	1	10-bit : left justified : signed	$7F:$C0	$80:$00
0	1	X1	10-bit : right justified : unsigned	$03:$FF	$00:$00

 

 

 

1 The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.

2 8-bit results are always in ATD1RH.

 

 

 

PRS — Prescaler Rate Select

 

 

 

PRS	Factor = (PRS +1) × 2	Max Bus Clock MHz (2 MHz max ATD Clock)1	Max Bus Clock MHz (1 MHz max ATD Clock)2	Min Bus Clock3 MHz (500 kHz min ATD Clock)
0000	2	4	2	1
0001	4	8	4	2
0010	6	12	6	3
0011	8	16	8	4
0100	10	20	10	5
0101	12	20	12	6
0110	14	20	14	7
0111	16	20	16	8
1000	18	20	18	9
1001	20	20	20	10
1010	22	20	20	11
1011	24	20	20	12
1100	26	20	20	13
1101	28	20	20	14
1110	30	20	20	15
1111	32	20	20	16

 

 

 

¹            Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock frequency) × 2 (Factor) = 4 MHz.

²            Use these settings if the maximum desired ATD conversion clock frequency is 1 MHz. The max bus clock frequency is computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 1 (max ATD conversion clock frequency) × 2 (Factor) = 2 MHz.

³            Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock frequency) × 2 (Factor) = 1 MHz.

ATD Status and Control (ATD1SC)

对ATD status and control register的CCF清零，就会取消当前的中断，并开始一个新的转换

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	CCF	ATDIE	ATDCO	ATDCH
写	×
复位	0	0	0	0	0	0	0	1

 

 

 

CCF — Conversion Complete Flag

是只读位，在每次转换完成时被置1，当ATD1SC register写入数据的时候会被清零，在数据从ATD1RH或ATD1RL中读出的时候也会被清零

1 = Current conversion is complete.

0 = Current conversion is not complete.

 

 

 

ATDIE — ATD Interrupt Enabled

1 = ATD interrupt enabled.

0 = ATD interrupt disabled.

 

 

 

ATDCO — ATD Continuous Conversion

1 = Continuous conversion mode.

0 = Single conversion mode.

 

 

 

ATDCH — Analog Input Channel Select

ATDCH	Analog Input Channel
00	AD0
01	AD1
02	AD2
03	AD3
04	AD4
05	AD5
06	AD6
07	AD7
08–1D	Reserved ( default to VREFL)
1E	VREFH
1F	VREFL

 

 

 

ATD Result Data (ATD1RH, ATD1RL)

是只读的

 

 

 

ATD Pin Enable (ATD1PE)

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	ATDPE7	ATDPE6	ATDPE5	ATDPE4	ATDPE3	ATDPE2	ATDPE1	ATDPE0
写
复位	0	0	0	0	0	0	0	0

ATD pin enable register用来配置作为ATD管脚，当对其写入，会中断当前的转换，但是不会开始新的转换。如果ATDPEx 是 0 (disabled for ATD usage)但是相应的ATDCH即使是选定的，ATD也不会进行只会往ATD result registers里写入0

1 = Pin enabled for ATD usage.

0 = Pin disabled for ATD usage.