MC9S08GT60(3)

Serial Peripheral Interface (SPI) Module

 

 

 

 

 

 

SPI Control Register 1 (SPI1C1)

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	SPIE	SPE	SPTIE	MSTR	CPOL	CPHA	SSOE	LSBFE
写
复位	0	0	0	0	0	1	0	0

SPI Control Register 1 (SPI1C1)

 

 

 

 

 

 

SPIE— SPI Interrupt Enable (for SPRF and MODF)

1 = When SPRF or MODF is 1, request a hardware interrupt.

0 = Interrupts from SPRF and MODF inhibited (use polling).

SPE — SPI System Enable

1 = SPI system enabled.

0 = SPI system inactive.

SPTIE— SPI Transmit Interrupt Enable

1 = When SPTEF is 1, hardware interrupt requested.

0 = Interrupts from SPTEF inhibited (use polling).

MSTR — Master/Slave Mode Select

1 = SPI module configured as a master SPI device.

0 = SPI module configured as a slave SPI device.

CPOL— Clock Polarity

1 = Active-low SPI clock (idles high).

0 = Active-high SPI clock (idles low).

CPHA— Clock Phase

1 = First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer.

0 = First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer.

SSOE — Slave Select Output Enable

MODFEN	SSOE	Master Mode	Slave Mode
0	0	General-purpose I/O (not SPI)	Slave select input
0	1	General-purpose I/O (not SPI)	Slave select input
1	0	SS input for mode fault	Slave select input
1	1	Automatic SS output	Slave select input

 

 

 

 

 

 

LSBFE— LSB First (Shifter Direction)

1 = SPI serial data transfers start with least significant bit.

0 = SPI serial data transfers start with most significant bit.

SPI Control Register 2 (SPI1C2)

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	0	0	0	MODFEN	BIDIROE	0	SPISWAI	SPC0
写	×	×	×			×
复位	0	0	0	0	0	0	0	0

MODFEN— Master Mode-Fault Function Enable

1 = Mode fault function enabled, master SS1 pin acts as the mode fault input or the slave select output.

0 = Mode fault function disabled, master SS1 pin reverts to general-purpose I/O not controlled by SPI.

BIDIROE — Bidirectional Mode Output Enable

1 = SPI I/O pin enabled as an output.

0 = Output driver disabled so SPI data I/O pin acts as an input.

SPISWAI — SPI Stop in Wait Mode

1 = SPI clocks stop when the MCU enters wait mode.

0 = SPI clocks continue to operate in wait mode.

SPC0 — SPI Pin Control 0

1 = SPI configured for single-wire bidirectional operation.

0 = SPI uses separate pins for data input and data output.

 

 

 

 

 

 

SPI Baud Rate Register (SPI1BR)

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	0	SPPR2	SPPR1	SPPR0	0	SPR2	SPR1	SPR0
写	×				×
复位	0	0	0	0	0	0	0	0

 

 

 

 

 

 

SPPR2:SPPR1:SPPR0 — SPI Baud Rate Prescale Divisor

SPPR2:SPPR1:SPPR0	Prescaler Divisor
0:0:0	1
0:0:1	2
0:1:0	3
0:1:1	4
1:0:0	5
1:0:1	6
1:1:0	7
1:1:1	8

 

 

 

 

 

 

SPR2:SPR1:SPR0 — SPI Baud Rate Divisor

SPR2:SPR1:SPR0	Rate Divisor
0:0:0	2
0:0:1	4
0:1:0	8
0:1:1	16
1:0:0	32
1:0:1	64
1:1:0	128
1:1:1	256

 

 

 

 

 

 

SPI Status Register (SPI1S)

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	SPRF	0	0	SPTEF	MODF	0	0	0
写	×	×	×	×	×	×	×	×
复位	0	0	0	0	0	0	0	0

 

 

 

 

 

 

SPRF — SPI Read Buffer Full Flag

1 = Data available in the receive data buffer.

0 = No data available in the receive data buffer.

SPTEF — SPI Transmit Buffer Empty Flag

1 = SPI transmit buffer empty.

0 = SPI transmit buffer not empty.

MODF — Master Mode Fault Flag

1 = Mode fault error detected.

0 = No mode fault error.

 

 

 

 

 

 

SPI Data Register (SPI1D)

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
写
复位	0	0	0	0	0	0	0	0

SPI Data Register (SPI1D)