MC9S08GT60(2)

Timer/PWM (TPM) Module

The TPM includes:

• An 8-bit status and control register (TPMxSC)

• A 16-bit counter (TPMxCNTH:TPMxCNTL)

• A 16-bit modulo register (TPMxMODH:TPMxMODL)

Each timer channel has:

• An 8-bit status and control register (TPMxCnSC)

• A 16-bit channel value register (TPMxCnVH:TPMxCnVL)

 

 

 

 

Timer x Status and Control Register (TPMxSC)

	Bit7	Bit6	Bi5	Bit4	Bit3	Bit2	Bit1	Bit0
读	TOF	TOIE	CPWMS	CLKSB	CLKSA	PS2	PS1	PS0
写	×
复位	0	0	0	0	0	0	0	0

 

 

 

 

TOF — Timer Overflow Flag

TPM counter会在到达TPM counter modulo registers的预定值的时候置为$0000同时将TOF置成1

1 = TPM counter has overflowed.

0 = TPM counter has not reached modulo value or overflow.

TOIE— Timer Overflow Interrupt Enable

1 = TOF interrupts enabled.

0 = TOF interrupts inhibited (use software polling).

CPWMS— Center-Aligned PWM Select

1 = All TPMx channels operate in center-aligned PWM mode.

0 = All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the MSnB:MSnA control bits in each channel’s status and control register.

 

 

 

 

 

 

 

 

CLKSB:CLKSA — Clock Source Select

用来允许TPM或者选择驱动计数器的时钟

CLKSB:CLKSA	TPM Clock Source to Prescaler Input
0:0	No clock selected (TPM disabled)
0:1	Bus rate clock (BUSCLK)
1:0	Fixed system clock (XCLK)
1:1	External source (TPMx Ext Clk)12

¹      The maximum frequency that is allowed as an external clock is one-fourth of the bus frequency.

²      When the TPMxCH0 pin is selected as the TPM clock source, the corresponding ELS0B:ELS0A control bits should be set to 0:0 so channel 0 does not try to use the same pin for a conflicting function.

PS2:PS1:PS0 — Prescale Divisor Select

PS2:PS1:PS0	TPM Clock Source Divided-By
0:0:0	1
0:0:1	2
0:1:0	4
0:1:1	8
1:0:0	16
1:0:1	32
1:1:0	64
1:1:1	128

 

 

 

 

Timer x Counter Registers (TPMxCNTH:TPMxCNTL)

读取两个寄存器的高字节或者低字节中的任意一个会使得其他一个被锁存，直到另一个字节被读出。

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit15	Bit14	Bit13	Bit12	Bit11	Bit10	Bit9	Bit8
写	Any write to TPMxCNTH clears the 16-bit counter
复位	0	0	0	0	0	0	0	0

Timer x Counter Register High (TPMxCNTH)

 

 

 

 

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
写	Any write to TPMxCNTL clears the 16-bit counter
复位	0	0	0	0	0	0	0	0

Timer x Counter Register Low (TPMxCNTL)

 

 

 

 

Timer x Counter Modulo Registers (TPMxMODH:TPMxMODL)

用来设定计数器的溢出值，当计数器到达设定的值的时候，TOF会被置1，同时计数器会在根据CPWMS的不同作出不同的选择。当CPWMS＝0时计数器在下一个时钟开始的时候从$0000从新开始计数，当CPWMS＝1计数器会开始递减

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit15	Bit14	Bit13	Bit12	Bit11	Bit10	Bit9	Bit8
写
复位	0	0	0	0	0	0	0	0

Timer x Counter Modulo Register High (TPMxMODH)

 

 

 

 

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
写
复位	0	0	0	0	0	0	0	0

Timer x Counter Modulo Register Low (TPMxMODL)

 

 

 

 

Timer x Channel n Status and Control Register (TPMxCnSC)

 

 

 

 

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	CHnF	CHnIE	MSnB	MSnA	ELSnB	ELSnA	0	0
写							×	×
复位	0	0	0	0	0	0	0	0

 

 

 

 

CHnF — Channel n Flag

当channel n用作输入捕捉时，CHnF会在跳变沿被置1。当channel n用作输出比较或者边缘PWM时，CHnF会在TPM counter registers 的值和 TPM channel n value registers匹配时被置1。这一位很少用在中心PWM上

1 = Input capture or output compare event occurred on channel n.

0 = No input capture or output compare event occurred on channel n.

CHnIE — Channel n Interrupt Enable

1 = Channel n interrupt requests enabled.

0 = Channel n interrupt requests disabled (use software polling).

MSnB— Mode Select B for TPM Channel n

MSnA— Mode Select A for TPM Channel n

ELSnB:ELSnA — Edge/Level Select Bits

CPWMS	MSnB:MSnA	ELSnB:ELSnA	Mode	Configuration
X	XX	00	Pin not used for TPM channel; use as an external clock for the TPM or revert to general-purpose I/O
0	00	01	Input capture	Capture on rising edge only
		10		Capture on falling edge only
		11		Capture on rising or falling edge
	01	00	Output compare	Software compare only
		01		Toggle output on compare
		10		Clear output on compare
		11		Set output on compare
	1X	10	Edge-aligned PWM	High-true pulses (clear output on compare)
		X1		Low-true pulses (set output on compare)
1	XX	10	Center-aligned PWM	High-true pulses (clear output on compare-up)
		X1		Low-true pulses (set output on compare-up)

 

 

 

 

Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)

 

 

 

 

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit15	Bit14	Bit13	Bit12	Bit11	Bit10	Bit9	Bit8
写
复位	0	0	0	0	0	0	0	0

Timer x Channel Value Register High (TPMxCnVH)

 

 

 

 

	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
读	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
写
复位	0	0	0	0	0	0	0	0

Timer x Channel Value Register Low (TPMxCnVL)