[RK3399][Android7.1] 调试笔记 --- TC358775在uboot中的显示驱动patch

Platform: RK3399
OS: Android 7.1
Kernel: v4.4.83

二话不说，直接贴Patch.

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 432e3ff..934608f 100755
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -46,7 +46,7 @@ obj-$(CONFIG_ROCKCHIP_DISPLAY) += rockchip_display.o rockchip_crtc.o \
 			rockchip_phy.o
 obj-$(CONFIG_ROCKCHIP_VOP) += rockchip_vop.o rockchip_vop_reg.o
 obj-$(CONFIG_ROCKCHIP_MIPI_DSI)	+= rockchip_mipi_dsi.o
-obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += rockchip-dw-mipi-dsi.o rockchip-inno-mipi-dphy.o
+obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += rockchip_dsi.o rockchip-inno-mipi-dphy.o
 obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += rockchip_analogix_dp.o rockchip_analogix_dp_reg.o
 obj-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi/
diff --git a/drivers/video/rockchip_connector.c b/drivers/video/rockchip_connector.c
index c09045c..1a86ef2 100644
--- a/drivers/video/rockchip_connector.c
+++ b/drivers/video/rockchip_connector.c
@@ -22,21 +22,21 @@
 static const struct rockchip_connector g_connector[] = {
 #ifdef CONFIG_ROCKCHIP_DW_MIPI_DSI
 	{
-	 .compatible = "rockchip,rk3288-mipi-dsi",
-	 .funcs = &rockchip_dw_mipi_dsi_funcs,
-	 .data = &rk3288_mipi_dsi_drv_data,
-	},{
-	 .compatible = "rockchip,rk3366-mipi-dsi",
-	 .funcs = &rockchip_dw_mipi_dsi_funcs,
-	 .data = &rk3366_mipi_dsi_drv_data,
-	},{
-	 .compatible = "rockchip,rk3368-mipi-dsi",
-	 .funcs = &rockchip_dw_mipi_dsi_funcs,
-	 .data = &rk3368_mipi_dsi_drv_data,
-	},{
-	 .compatible = "rockchip,rk3399-mipi-dsi",
-	 .funcs = &rockchip_dw_mipi_dsi_funcs,
-	 .data = &rk3399_mipi_dsi_drv_data,
+	 .compatible = "rockchip,rk3288-dsi",
+	 .funcs = &rockchip_dsi_connector_funcs,
+	 .data = &rk3288_dsi_soc_data,
+	}, {
+	 .compatible = "rockchip,rk3366-dsi",
+	 .funcs = &rockchip_dsi_connector_funcs,
+	 .data = &rk3366_dsi_soc_data,
+	}, {
+	 .compatible = "rockchip,rk3368-dsi",
+	 .funcs = &rockchip_dsi_connector_funcs,
+	 .data = &rk3368_dsi_soc_data,
+	}, {
+	 .compatible = "rockchip,rk3399-dsi",
+	 .funcs = &rockchip_dsi_connector_funcs,
+	 .data = &rk3399_dsi_soc_data,
 	},
 #endif
 #ifdef CONFIG_ROCKCHIP_ANALOGIX_DP
diff --git a/drivers/video/rockchip_connector.h b/drivers/video/rockchip_connector.h
index eb6c9f2..4bf3197 100644
--- a/drivers/video/rockchip_connector.h
+++ b/drivers/video/rockchip_connector.h
@@ -68,12 +68,12 @@ const struct rockchip_connector *
 rockchip_get_connector(const void *blob, int connector_node);
 
 #ifdef CONFIG_ROCKCHIP_DW_MIPI_DSI
-struct dw_mipi_dsi_plat_data;
-extern const struct rockchip_connector_funcs rockchip_dw_mipi_dsi_funcs;
-extern const struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data;
-extern const struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data;
-extern const struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data;
-extern const struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data;
+struct rockchip_dsi_soc_data;
+extern const struct rockchip_connector_funcs rockchip_dsi_connector_funcs;
+extern const struct rockchip_dsi_soc_data rk3288_dsi_soc_data;
+extern const struct rockchip_dsi_soc_data rk3366_dsi_soc_data;
+extern const struct rockchip_dsi_soc_data rk3368_dsi_soc_data;
+extern const struct rockchip_dsi_soc_data rk3399_dsi_soc_data;
 #endif
 #ifdef CONFIG_ROCKCHIP_ANALOGIX_DP
 struct rockchip_dp_chip_data;
diff --git a/drivers/video/rockchip_dsi.c b/drivers/video/rockchip_dsi.c
new file mode 100644
index 0000000..e76017d
--- /dev/null
+++ b/drivers/video/rockchip_dsi.c
@@ -0,0 +1,1643 @@
+/*
+ * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <resource.h>
+#include <asm/arch/rkplat.h>
+#include <asm/unaligned.h>
+#include <linux/list.h>
+#include <div64.h>
+
+#include "rockchip_display.h"
+#include "rockchip_crtc.h"
+#include "rockchip_connector.h"
+#include "rockchip_phy.h"
+#include "rockchip_mipi_dsi.h"
+
+#define GRF_DESC(r, h, l)     ((r << 16) | (h << 8) | (l))
+
+#define IS_DSI0(dsi)	((dsi)->id == 0)
+#define IS_DSI1(dsi)	((dsi)->id == 1)
+
+/* DWC MIPI DSI Host Controller Register and Field Descriptions */
+#define DSI_VERSION			0x000
+#define DSI_PWR_UP			0x004
+#define RESET				0
+#define POWER_UP			BIT(0)
+#define DSI_CLKMGR_CFG			0x008
+#define TO_CLK_DIVIDSION_MASK		GENMASK(15, 8)
+#define TO_CLK_DIVIDSION(x)		UPDATE(x, 15, 8)
+#define TX_ESC_CLK_DIVIDSION_MASK	GENMASK(7, 0)
+#define TX_ESC_CLK_DIVIDSION(x)		UPDATE(x, 7, 0)
+#define DSI_DPI_VCID			0x00c
+#define DPI_VCID(x)			UPDATE(x, 1, 0)
+#define DSI_DPI_COLOR_CODING		0x010
+#define LOOSELY18_EN(x)			UPDATE(x, 8, 8)
+#define DPI_COLOR_CODING(x)		UPDATE(x, 3, 0)
+#define DSI_DPI_CFG_POL			0x014
+#define COLORM_ACTIVE_LOW		BIT(4)
+#define SHUTD_ACTIVE_LOW		BIT(3)
+#define HSYNC_ACTIVE_LOW		BIT(2)
+#define VSYNC_ACTIVE_LOW		BIT(1)
+#define DATAEN_ACTIVE_LOW		BIT(0)
+#define DSI_DPI_LP_CMD_TIM		0x018
+#define DSI_PCKHDL_CFG			0x02c
+#define CRC_RX_EN			BIT(4)
+#define ECC_RX_EN			BIT(3)
+#define BTA_EN				BIT(2)
+#define EOTP_RX_EN			BIT(1)
+#define EOTP_TX_EN_MASK			BIT(0)
+#define EOTP_TX_EN			BIT(0)
+#define DSI_GEN_VCID			0x030
+#define GEN_VCID_RX(x)			UPDATE(x, 1, 0)
+#define DSI_MODE_CFG			0x034
+#define COMMAND_MODE			BIT(0)
+#define VIDEO_MODE			0
+#define DSI_VID_MODE_CFG		0x038
+#define VPG_ORIENTATION(x)		UPDATE(x, 24, 24)
+#define VPG_MODE(x)			UPDATE(x, 20, 20)
+#define VPG_EN				BIT(16)
+#define LP_CMD_EN			BIT(15)
+#define FRAME_BTA_ACK_EN(x)		BIT(14)
+#define LP_HFP_EN			BIT(13)
+#define LP_HBP_EN			BIT(12)
+#define LP_VACT_EN			BIT(11)
+#define LP_VFP_EN			BIT(10)
+#define LP_VBP_EN			BIT(9)
+#define LP_VSA_EN			BIT(8)
+#define VID_MODE_TYPE(x)		UPDATE(x, 1, 0)
+#define NON_BURST_MODE_SYNC_PULSE	0
+#define NON_BURST_MODE_SYNC_EVENT	1
+#define BURST_MODE			2
+#define DSI_VID_PKT_SIZE		0x03c
+#define VID_PKT_SIZE(x)			UPDATE(x, 13, 0)
+#define DSI_VID_NUM_CHUMKS		0x040
+#define DSI_VID_NULL_PKT_SIZE		0x044
+#define DSI_VID_HSA_TIME		0x048
+#define VID_HSA_TIME(x)			UPDATE(x, 11, 0)
+#define DSI_VID_HBP_TIME		0x04c
+#define VID_HBP_TIME(x)			UPDATE(x, 11, 0)
+#define DSI_VID_HLINE_TIME		0x050
+#define VID_HLINE_TIME(x)		UPDATE(x, 14, 0)
+#define DSI_VID_VSA_LINES		0x054
+#define VSA_LINES(x)			UPDATE(x, 9, 0)
+#define DSI_VID_VBP_LINES		0x058
+#define VBP_LINES(x)			UPDATE(x, 9, 0)
+#define DSI_VID_VFP_LINES		0x05c
+#define VFP_LINES(x)			UPDATE(x, 9, 0)
+#define DSI_VID_VACTIVE_LINES		0x060
+#define V_ACTIVE_LINES(x)		UPDATE(x, 13, 0)
+#define DSI_CMD_MODE_CFG		0x068
+#define CMD_XFER_TYPE_MASK		0x010F7F00
+#define CMD_XFER_TYPE_LP		0x010F7F00
+#define CMD_XFER_TYPE_HS		0
+#define ACK_RQST_EN_MASK		BIT(1)
+#define ACK_RQST_EN			BIT(1)
+#define TEAR_FX_EN_MASK			BIT(0)
+#define TEAR_FX_EN			BIT(0)
+#define DSI_GEN_HDR			0x06c
+#define DSI_GEN_PLD_DATA		0x070
+#define DSI_CMD_PKT_STATUS		0x074
+#define GEN_RD_CMD_BUSY			BIT(6)
+#define GEN_PLD_R_FULL			BIT(5)
+#define GEN_PLD_R_EMPTY			BIT(4)
+#define GEN_PLD_W_FULL			BIT(3)
+#define GEN_PLD_W_EMPTY			BIT(2)
+#define GEN_CMD_FULL			BIT(1)
+#define GEN_CMD_EMPTY			BIT(0)
+#define DSI_TO_CNT_CFG			0x078
+#define HSTX_TO_CNT(x)			UPDATE(x, 31, 16)
+#define LPRX_TO_CNT(x)			UPDATE(x, 15, 0)
+#define DSI_HS_RD_TO_CNT		0x07c
+#define DSI_LP_RD_TO_CNT		0x080
+#define DSI_HS_WR_TO_CNT		0x084
+#define DSI_LP_WR_TO_CNT		0x088
+#define DSI_BTA_TO_CNT			0x08c
+#define DSI_LPCLK_CTRL			0x094
+#define AUTO_CLKLANE_CTRL_MASK		BIT(1)
+#define AUTO_CLKLANE_CTRL		BIT(1)
+#define PHY_TXREQUESTCLKHS_MASK		BIT(0)
+#define PHY_TXREQUESTCLKHS		BIT(0)
+#define DSI_PHY_TMR_LPCLK_CFG		0x098
+#define PHY_CLKHS2LP_TIME(x)		UPDATE(x, 25, 16)
+#define PHY_CLKLP2HS_TIME(x)		UPDATE(x, 9, 0)
+#define DSI_PHY_TMR_CFG			0x09c
+#define PHY_HS2LP_TIME(x)		UPDATE(x, 31, 24)
+#define PHY_LP2HS_TIME(x)		UPDATE(x, 23, 16)
+#define MAX_RD_TIME(x)			UPDATE(x, 14, 0)
+#define DSI_PHY_RSTZ			0x0a0
+#define PHY_ENABLECLK_MASK		BIT(2)
+#define PHY_ENABLECLK			BIT(2)
+#define PHY_RSTZ_MASK			BIT(1)
+#define PHY_RSTZ			BIT(1)
+#define PHY_SHUTDOWNZ_MASK		BIT(0)
+#define PHY_SHUTDOWNZ			BIT(0)
+#define DSI_PHY_IF_CFG			0x0a4
+#define PHY_STOP_WAIT_TIME(x)		UPDATE(x, 15, 8)
+#define N_LANES(x)			UPDATE(x, 1, 0)
+#define DSI_PHY_STATUS			0x0b0
+#define PHY_ULPSACTIVENOT3LANE		BIT(12)
+#define PHY_STOPSTATE3LANE		BIT(11)
+#define PHY_ULPSACTIVENOT2LANE		BIT(10)
+#define PHY_STOPSTATE2LANE		BIT(9)
+#define PHY_ULPSACTIVENOT1LANE		BIT(8)
+#define PHY_STOPSTATE1LANE		BIT(7)
+#define PHY_ULPSACTIVENOT0LANE		BIT(5)
+#define PHY_STOPSTATE0LANE		BIT(4)
+#define PHY_ULPSACTIVENOTCLK		BIT(3)
+#define PHY_STOPSTATECLKLANE		BIT(2)
+#define PHY_DIRECTION			BIT(1)
+#define PHY_LOCK			BIT(0)
+#define PHY_STOPSTATELANE		(PHY_STOPSTATE0LANE | \
+					 PHY_STOPSTATECLKLANE)
+#define DSI_PHY_TST_CTRL0		0x0b4
+#define PHY_TESTCLK_MASK		BIT(1)
+#define PHY_TESTCLK			BIT(1)
+#define PHY_TESTCLR_MASK		BIT(0)
+#define PHY_TESTCLR			BIT(0)
+#define DSI_PHY_TST_CTRL1		0x0b8
+#define PHY_TESTEN_MASK			BIT(16)
+#define PHY_TESTEN			BIT(16)
+#define PHY_TESTDOUT_SHIFT		8
+#define PHY_TESTDIN_MASK		GENMASK(7, 0)
+#define PHY_TESTDIN(x)			UPDATE(x, 7, 0)
+#define DSI_INT_ST0			0x0bc
+#define DSI_INT_ST1			0x0c0
+#define DSI_INT_MSK0			0x0c4
+#define DSI_INT_MSK1			0x0c8
+
+/* PLL Bias Current Selector/Filter Capacitance Control/VCO Control */
+#define VCO_RANGE_PROGRAM_EN	BIT(7)
+#define VCO_RANGE_CTRL(x)	UPDATE(x, 5, 3)
+#define VCO_INTER_CAP_CTRL(x)	UPDATE(x, 2, 1)
+/* PLL CP Control / PLL Lock Bypass for Initialization and for ULP */
+#define CP_CURRENT(x)		UPDATE(x, 3, 0)
+/* PLL LPF and CP Control */
+#define CP_PROGRAM_EN		BIT(7)
+#define LPF_PROGRAM_EN		BIT(6)
+#define LPF_RESISTORS(x)	UPDATE(x, 5, 0)
+/* PLL Input Divider Ratio */
+#define INPUT_DIV(x)		UPDATE(x, 6, 0)
+/* PLL Loop Divider Ratio */
+#define LOW_PROGRAM_EN		0
+#define HIGH_PROGRAM_EN		BIT(7)
+#define LOOP_DIV_4_0(x)		UPDATE(x, 4, 0)
+#define LOOP_DIV_8_5(x)		UPDATE(x, 3, 0)
+/* PLL Input and Loop Divider Ratios Control */
+#define LOOP_DIV_PROGRAM_EN	BIT(5)
+#define INPUT_DIV_PROGRAM_EN	BIT(4)
+/* Bandgap and Bias Control */
+#define OVERRIDE_ENBALE		BIT(6)
+#define BIAS_BLOCK_POWER_ON	BIT(2)
+#define BANDGAP_POWER_ON	BIT(0)
+/* AFE/BIAS/Bandgap Analog Progr