TMS320C6678开发笔记---SRIO例程1

15节  SRIO例程

参考文档:(系列博客,对官方SRIO手册的中文解释)

https://blog.csdn.net/kunkliu/article/details/105271629

创龙提供的SRIO中文参考资料《C66x串行快速输入输出(SRIO)用户指南.pdf》

TI官方资料《Serial Rapid IO (SRIO) User Guide.pdf》

 

15.1节  K1_STK_v1.1回环测试例程

K1_STK_v1.1 中参考文档:(建议看一下)

《KeyStone_1_SRIO_STK_User's_Guide.doc》---理解SRIO回环测试原理

 

15.1.1   仿真不能定位到main函数

  • 下图的platform和XDCtools有直接关系,版本要对应

15.2节  回环测试方法

  • Digital loopback Test(外部不需要接线)

  • Serdes loopback test(外部不需要接线)

  • External loopback test(外部需要接线

15.3节  创龙例程SYSBIOS_SRIO_Device01分析

  • 硬件信息介绍

板卡上有4颗DSP6678,每颗6678的SRIO连接到桥片1848。

  • 工程介绍

SYSBIOS_SRIO_Device01与SYSBIOS_SRIO_Device02配合使用完成SRIO数据传输,Device01主动向Device02 Nwrite写数据,Device02通过写数据的最后一个字节判断是否Nwrite完成,然后Device02将收到的数据乘10后,将数据通过Nwrite写回到Device01,Device01也通过写数据的最后一个字节判断是否Nwrite完成,循环上述过程。

  • 工程编译
/*
 * CCSv7 IDE
 * 7.4
 *
 * 依赖组件版本为
 * - XDCTools 3.50.5.12-core *
 * - NDK 2.25.1.11 *
 * - SYS/BIOS 6.52.0.12 *
 * - UIA 2.20.0.02 *
 * - Tronlong.DSP.C6000.C66x
 */
  • SRIO初始化代码如下:
void SRIOInit()
{
	// 使能外设
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_SRIO, PSC_MDCTL_NEXT_ENABLE, PSC_POWERDOMAIN_SRIO, PSC_PDCTL_NEXT_ON);
    // 禁用 SRIO 及 SRIO Block
    SRIOGlobalDisable();
	int i;
   	for(i = 0; i <= 9; i++)
   	{
   		SRIOBlockDisable(i);
   	}
    // 设置 Boot Complete 为 0 以便可以修改 SRIO 所有寄存器包括只读(Read Only)寄存器
   	SRIOBootCompleteSet(SRIO_Disable);
    // 使能 SRIO 及 SRIO Block
    SRIOGlobalEnable();
   	for(i = 0; i <= 9; i++)
   	{
   		SRIOBlockEnable(i);
   	}
    // 配置 SRIO Lane 工作模式
   	SRIOModeSet(0, SRIO_Normal);
   	SRIOModeSet(1, SRIO_Normal);
   	SRIOModeSet(2, SRIO_Normal);
   	SRIOModeSet(3, SRIO_Normal);
	// 使能自动优先级提升
   	SRIOAutomaticPriorityPromotionEnable();
	// 设置 SRIO VBUS 预分频为 44.7 到 89.5
   	SRIOPrescalarSelectSet(0);
	// 解锁关键寄存器
	KickUnlock();
    // 配置 SRIO SerDes 时钟(156.25Mhz x 16 = 2.5GHz)
    SRIOSerDesPLLSet(0x81); // 5G
    // 配置 SRIO SerDes 发送 / 接收
    // 数据率 5Gbps(8B/10B)
    SRIOSerDesTxSet(0, 0x001C8F95);     //0x00180795   0x001C8F95
    SRIOSerDesTxSet(1, 0x001C8F95);
    SRIOSerDesTxSet(2, 0x001C8F95);
    SRIOSerDesTxSet(3, 0x001C8F95);
    SRIOSerDesRxSet(0, 0x00468495);     //0x00440495  0x00468495
    SRIOSerDesRxSet(1, 0x00468495);
    SRIOSerDesRxSet(2, 0x00468495);
    SRIOSerDesRxSet(3, 0x00468495);
    // 等待 SRIO SerDes 锁定
    while(!(SRIOSerDesPLLStatus() & 0x1));
	// 锁定关键寄存器
	KickLock();
    // 设置设备信息
   	SRIODeviceInfoSet(DEVICE_ID1_8BIT, 0x50, DEVICE_REVISION);
    // 设置组织信息
   	SRIOAssemblyInfoSet(DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID, DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);
   	// PE 特性配置
    SRIOProcessingElementFeaturesSet(0x20000199);
    // 配置源及目标操作
    SRIODestinationOperationsSet(0x0004FDF4);
    SRIODestinationOperationsSet(0x0000FC04);
    // 设置 SRIO 设备 ID
    SRIODeviceIDSet(DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);
    // 配置 TLM 基本路由信息
    SRIOTLMPortBaseRoutingSet(SRIO_Port0, 1, SRIO_Enable, SRIO_Enable, SRIO_Disable);
    SRIOTLMPortBaseRoutingPatternMatchSet(SRIO_Port0, 1, DEVICE_ID2_8BIT, 0xFF);
    // 配置端口 PLM
	// 配置 PLM 端口 Silence Timer
	SRIOPLMPortSilenceTimerSet(SRIO_Port0, 0x2);
	// 使能端口
	SRIOInputPortEnable(SRIO_Port0);
	SRIOOutputPortEnable(SRIO_Port0);
	// 配置 PLM 端口 Discovery Timer
	SRIOPLMPortDiscoveryTimerSet(SRIO_Port0, 0x2);
	// 配置端口 Write Reception Capture
	SRIOPortWriteRxCapture(SRIO_Port0, 0x0);
    // 配置端口连接超时
	SRIOPortLinkTimeoutSet(0x000FFF);
    // 端口 Master 使能
	SRIOPortGeneralSet(SRIO_Enable, SRIO_Enable, SRIO_Disable);
    // 清除 Sticky Register 位
	SRIORegisterResetControlClear();
	// 设置端口写 ID
	SRIOPortWriteTargetDeviceID(0, DEVICE_ID2_8BIT, SRIO_ID_8Bit);
    // 设置数据流最大传输单元(MTU)
	SRIODataDtreamingLogicalLayerControl(64);
	// 配置端口路由模式
	SRIOPLMPathModeControl(SRIO_Port0, SRIO_Mode4_1_4x);
    // 设置 LLM Port IP 预分频
	SRIOServerClockPortIPPrescalar(0x1F);
	// 使能外设
	SRIOPeripheralEnable();
    // 配置完成
   	SRIOBootCompleteSet(SRIO_Enable);
    // 检查端口是否就绪
    while(SRIOPortOKCheck(SRIO_Port0) != TRUE);
}
  • main函数中接收数据部分代码,以Device02介绍

  • 程序运行方法:
  1. 将SYSBIOS_SRIO_Device01加载到dsp0的0核,SYSBIOS_SRIO_Device02加载到dsp1 的0核
  2. 先运行dsp1的SYSBIOS_SRIO_Device02,在运行dsp0的SYSBIOS_SRIO_Device01
  • console打印信息如下:

  • device01 与device02的0x90000000内存值均为如下图:

15.4节  创龙例程SYSBIOS_SRIO_Device01v2分析

在上一节基础上增加了门铃的代码。调了好久才把门铃调通,SYSBIOS_SRIO_Device01v2与SYSBIOS_SRIO_Device02v2修改部分基本一致,下面将修改部分一一列出:

  • cfg文件修改:

对应包含的头文件修改如下:

  • SRIOInit初始化代码如下:
void SRIOInit()
{
	// 使能外设
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_SRIO, PSC_MDCTL_NEXT_ENABLE, PSC_POWERDOMAIN_SRIO, PSC_PDCTL_NEXT_ON);
    // 禁用 SRIO 及 SRIO Block
    SRIOGlobalDisable();
	int i;
   	for(i = 0; i <= 9; i++)
   	{
   		SRIOBlockDisable(i);
   	}
    // 设置 Boot Complete 为 0 以便可以修改 SRIO 所有寄存器包括只读(Read Only)寄存器
   	SRIOBootCompleteSet(SRIO_Disable);
    // 使能 SRIO 及 SRIO Block
    SRIOGlobalEnable();
   	for(i = 0; i <= 9; i++)
   	{
   		SRIOBlockEnable(i);
   	}
    // 配置 SRIO Lane 工作模式
   	SRIOModeSet(0, SRIO_Normal);
   	SRIOModeSet(1, SRIO_Normal);
   	SRIOModeSet(2, SRIO_Normal);
   	SRIOModeSet(3, SRIO_Normal);
	// 使能自动优先级提升
   	SRIOAutomaticPriorityPromotionEnable();
	// 设置 SRIO VBUS 预分频为 44.7 到 89.5
   	SRIOPrescalarSelectSet(0);
	// 解锁关键寄存器
	KickUnlock();
    // 配置 SRIO SerDes 时钟(156.25Mhz x 16 = 2.5GHz)
    SRIOSerDesPLLSet(0x81);  // 5G
    // 配置 SRIO SerDes 发送 / 接收
    // 数据率 5Gbps(8B/10B)
    SRIOSerDesTxSet(0, 0x001C8F95);
    SRIOSerDesTxSet(1, 0x001C8F95);
    SRIOSerDesTxSet(2, 0x001C8F95);
    SRIOSerDesTxSet(3, 0x001C8F95);
    SRIOSerDesRxSet(0, 0x00468495);
    SRIOSerDesRxSet(1, 0x00468495);
    SRIOSerDesRxSet(2, 0x00468495);
    SRIOSerDesRxSet(3, 0x00468495);
    // 等待 SRIO SerDes 锁定
    while(!(SRIOSerDesPLLStatus() & 0x1));
	// 锁定关键寄存器
	KickLock();
    // 设置设备信息
   	SRIODeviceInfoSet(DEVICE_ID1_8BIT, 0x50, DEVICE_REVISION);
    // 设置组织信息
   	SRIOAssemblyInfoSet(DEVICE_ASSEMBLY_ID, DEVICE_ASSEMBLY_VENDOR_ID, DEVICE_ASSEMBLY_REVISION, DEVICE_ASSEMBLY_INFO);
   	// PE 特性配置
    SRIOProcessingElementFeaturesSet(0x20000199);
    // 配置源及目标操作
    SRIOSourceOperationsSet(0x0004FDF4);
    SRIODestinationOperationsSet(0x0000FC04);
    // 设置 SRIO 设备 ID
    SRIODeviceIDSet(DEVICE_ID1_8BIT, DEVICE_ID1_16BIT);
    // 配置 TLM 基本路由信息
    SRIOTLMPortBaseRoutingSet(SRIO_Port0, 1, SRIO_Enable, SRIO_Enable, SRIO_Disable);
    SRIOTLMPortBaseRoutingPatternMatchSet(SRIO_Port0, 1, DEVICE_ID2_8BIT, 0xFF);
    // 配置端口 PLM
	// 配置 PLM 端口 Silence Timer
	SRIOPLMPortSilenceTimerSet(SRIO_Port0, 0x2);
	// 使能端口
	SRIOInputPortEnable(SRIO_Port0);
	SRIOOutputPortEnable(SRIO_Port0);
	// 配置 PLM 端口 Discovery Timer
	SRIOPLMPortDiscoveryTimerSet(SRIO_Port0, 0x2);
	// 配置端口 Write Reception Capture
	SRIOPortWriteRxCapture(SRIO_Port0, 0x0);
    // 配置端口连接超时
	SRIOPortLinkTimeoutSet(0x000FFF);
    // 端口 Master 使能
	SRIOPortGeneralSet(SRIO_Enable, SRIO_Enable, SRIO_Disable);//实验发现必须第一个参数为enable,门铃才能中断,目前不知道原因何在
    // 清除 Sticky Register 位
	SRIORegisterResetControlClear();
	// 设置端口写 ID
	SRIOPortWriteTargetDeviceID(0, DEVICE_ID2_8BIT, SRIO_ID_8Bit);
    // 设置数据流最大传输单元(MTU)
	SRIODataDtreamingLogicalLayerControl(64);
	// 配置端口路由模式
	SRIOPLMPathModeControl(SRIO_Port0, SRIO_Mode4_1_4x);
    // 设置 LLM Port IP 预分频
	SRIOServerClockPortIPPrescalar(0x1F);
	// DoorBell 中断配置
	SRIODoorBellInterruptRoutingControl(SRIO_DoorBell_Dedicated_INT);
	// DoorBell 中断路由配置
	SRIODoorBellInterruptConditionRoutingSet(SRIO_DoorBell0, SRIO_DoorBellInt0, SRIO_IntDst_0_16);
	SRIODoorBellInterruptConditionRoutingSet(SRIO_DoorBell0, SRIO_DoorBellInt1, SRIO_IntDst_0_16);
	SRIODoorBellInterruptConditionRoutingSet(SRIO_DoorBell0, SRIO_DoorBellInt2, SRIO_IntDst_0_16);
	SRIODoorBellInterruptConditionRoutingSet(SRIO_DoorBell0, SRIO_DoorBellInt3, SRIO_IntDst_0_16);
	// 使能外设
	SRIOPeripheralEnable();
    // 配置完成
   	SRIOBootCompleteSet(SRIO_Enable);
}

 

  • main.c修改如下:

main.c基本应用逻辑没有修改,只是增加了一些打印信息,方便调试。主要修改点为,将SRIO DEVICE ID修改为了8 位的,对应发送接受配置时,ID的修改,此处不在一一列出。

  • 应用层逻辑如下:
  1. Device01v2和Device01v2启动后分别创建SRIODoorBellIsrDoorBellIntTsksmain
  2. Device01v2为主动发起者,启动后,SRIODoorBellIsr等待2.5s后,向Device02v2发送SRIO_DoorBell_Message_Notify01门铃中断。
  3. Device02v2收到门铃后,在中断函数中向DoorBellIntTsk发送信号量sem1,促使原先阻塞的DoorBellIntTsk运行,并向Device01v2发送SRIO_DoorBell_Message_Notify00门铃中断。
  4. Device01v2收到门铃后,在中断函数中向smain发送信号量sem,促使原先阻塞的smain运行,初始化发送数据,并向Device02v2发送SRIO_NWrite并且带有门铃,门铃类型为SRIO_DoorBell_Message_NWrite_Finished(此处没有明白为什么NWrite能和doorbell一起发送),然后smain又阻塞在sem信号量上。
  5. Device02v2此时能够收到Device01v2 NWrite的数据,又能够产生门铃中断,并在中断函数中发出sem信号量,促使原先阻塞的smain运行,然后将收到的数据乘10后,将数据向Device01v2发送SRIO_NWrite并且带有门铃,门铃类型为SRIO_DoorBell_Message_NWrite_Finishedsmain执行完成。
  6. Device01v2能够收到Device02v2 NWrite的数据,产生门铃中断,并在中断函数中发出sem信号量,促使原先阻塞的smain运行,对发送的数据与接收的数据比较,smain执行完成。

原本很简单的通讯流程被我写的有点繁琐。不过门铃工程中中断与信号量的配合使用还是值得学习的。

 

  • 程序运行方法:
  1. 将SYSBIOS_SRIO_Device01v2加载到dsp0的0核,SYSBIOS_SRIO_Device02v2加载到dsp1 的0核
  2. 先运行dsp1的SYSBIOS_SRIO_Device02v2,在运行dsp0的SYSBIOS_SRIO_Device01v2
  • console打印信息如下:

  • device01 与device02的0x90000000内存值均为如下图:

 

 

Core name: Xilinx LogiCORE Serial RapidIO Version: 5.5 Release Date: April 19, 2010 ================================================================================ This document contains the following sections: 1. Introduction 2. New Features 3. Supported Devices 4. Resolved Issues 5. Known Issues 6. Technical Support 7. Other Information (optional) 8. Core Release History 9. Legal Disclaimer ================================================================================ 1. INTRODUCTION For the most recent updates to the IP installation instructions for this core, please go to: http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm For system requirements: http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm This file contains release notes for the Xilinx LogiCORE IP Serial RapidIO v5.5 solution. For the latest core updates, see the product page at: http://www.xilinx.com/rapidio/ 2. NEW FEATURES - ISE 12.1 software support - Designed to RapidIO Interconnect Specification v2.1 - Virtex-6 LXT/HXT/SXT 5.0 Gbps support - Spartan-6 3.125 Gbps and 4x support - Expanded simulator support - Support for ML505, ML605 and SP605 boards (see Release Notes AR for details) 3. SUPPORTED DEVICES - Virtex-6 LXT/HXT/SXT/CXT - Spartan-6 LXT - Virtex-5 LXT/FXT/SXT - Virtex-4 FX 4. RESOLVED ISSUES - PHY does not properly pass CRF bit to Buffer - Version fixed : v5.5 - CR# 519603 - Updated PHY to properly pass CRF - GT settings for Spartan-6 and Virtex-6 updated based on characterization - Version fixed : v5.5 - PORT_INITIALIZED toggles indefinitely - Version fixed : v5.5 - CR# 551271 - GT wrappers updated so that the core will detect invalid data until RESETDONE asserts. - Processing Element Features CAR implemented incorrectly - Version fixed : v5.5 - CR# 528369 - Part of the PEF CAR was implemented in the PHY configuration space, now it is merged into the LOGIO configuration space as directed by the spec. See core User Guide for map of configuration space. - Recommended modifications to Example Design reset scheme - Version fixed : v5.5 - CR# 533208, 533209, 533212 - Updated reset sequence, see AR# 33574 for specifics. - Example design "implement.bat" file has error - Version fixed : v5.5 - CR# 533796 - Corrected syntax for NGDBuild command. - Virtex-6 clock modules not using production MMCM settings - Version fixed : v5.4rev1 - CR#546021 - Using outdated values from the clocking wizard in clock modules. - Buffer BRAM using READ_FIRST mode - Version fixed : v5.4rev1 - CR#546424 - Using READ_FIRST mode for buffer BRAMs - need to update to WRITE_FIRST mode for Spartan-6 and Virtex-6 based on characterization. - VHDL example design simulation error when CRF bit de-selected - Version fixed : v5.4rev1 - CR# 532020 - Updated example design so that CRF signals not added when CRF support is disabled. - Virtex-6 bring-up issues - Version fixed : v5.4 - CR#527725, CR#525309, CR#531695 - Using integer values for the MMCM_ADV, regenerated Virtex-6 wrappers based on general hardware characterization results, revised reset sequence. Please see core Release Notes for updates. - GUI settings incorrect or not properly reflected in hardware. - Version fixed : v5.4 - CR#507334, CR#528369, CR#528370 / AR#32122 - The following register fields were corrected: Re-transmit Suppression mask, Logical Layer extended features pointer, DeviceVendorID. - Latches inferred in VHDL example design - Version fixed: v5.2 - CR#509670 / AR#32189 - Added intermediate values for partial register and combinational assignments. - lnk_trdy_n does not assert in evaluation core simulations - Version fixed : v5.1rev1 - CR#493479 / AR#31864 - Modified initial state in evaluation cores. - PHY won't generate stand-alone due to missing module - Version fixed : v5.1rev1 - CR#493162 / AR#31834 - Shared file between buffer and log added to buffer file list. - Virtex-4 core has long initialization time - Version fixed : v5.1rev1 - CR#481684 / AR#31617 - Virtex-4 initSM modified to prevent branch to silent when RX PCS resets in DISCOVERY state. - LogIO local arbitration doesn't account for valid causing re-arbitration prior to legitimatepacket completion. - Version fixed : v5.1 - CR#478748 - Valid used to gate mresp_eof_n and iresp_eof_n for local arbitration. - A ireq_dsc_n asserted for an undefined packet type does not get propogated by the logical layer. - Version fixed : v5.1 - CR#478541 - undefined packet type decode now passes dsc to buffer allowing packet to be dropped. - 16-bit deviceID cores may see a maintenance response transaction presented but not validated on the IResp interface resulting in a lost transaction. by the logical layer. - Version fixed : v5.1 - CR#474894 - Fixed issue when the maintenance response is followed immediatly by a single DWord SWrite packet. - SourceID not configureable for IReq port. - Version fixed : v5.1 - CR#473938 - Added ireq_src_id port to logical layer. All transmit source IDs should now be configureable and all received destination IDs observable. - Write enables into LogIO registers aren't allowing partial register writes. - Version fixed : v5.1 - CR#473441 - Write enables now implementedfor all LogIO registers allowing byte-wise writes of CSRs such as the deviceID register and BAR. - Message response transaction received as a user defined packet type using 16-bit device IDs appears as a corrupted packet on the IResp interface. - Version fixed : v5.1 - CR#473400, CR#473693 - Fixed LogIO RX to properly handle all user-defined types. - PHY core does not dsc upon retry when coincident with TX packet eof resulting in potential buffer lock-up - Version fixed : v4.4rev2 - CR#478246 / AR#31407 - lnk_tdst_dsc_n now asserted for all retry and error scenarios. - Retry of packet being sent causes packet to get stuck in buffer - Version fixed : v4.4rev2 - CR#477217 / AR#31318 - No longer applicable, v5.1 introduces new buffer. - Core accepts muddled packet when reinitializing during packet receipt - Version fixed : v4.4rev1 - CR#477115 / AR#31308 - Core PNAs packet in receipt when link goes down. - Core LCSBA implementation removes 64MB of possible addressing space. - Version fixed : v4.4 - CR#472992 / AR#30939 - Use 10-bit mask with full 34-bit address for LCSBA intercept. - CRC error on stalled packet - Version fixed : v4.4 - CR#469678 / AR#30940 - Fixed condition which loaded in new CRC sequence on a stall just after sof received by PHY. This is a non-concern for Xilinx buffer users. - Virtex-4 4x core may intermittenly train down to 1x mode - Version fixed : v4.4 - CR#467616 / AR#30314 - Modified oplm_pcs_rst_sequence.v file supplied with the core to register asynchronous TXLOCK and RXLOCK signals. - Re-initialization not forced following a change to Port Width Override - Version fixed : v4.4 - CR#459427 / AR#30323 - Modified PHY Layer to detect a change in the port width override field and reinitialize when updated. - Messaging packets providing incorrect treq_byte_count value - Version fixed : v4.4 - CR#467116 / AR#30320 - Modified Logical Layer to properly decode Messaging size field. Modified testbench to properly check byte count for messaging type packets. - 8-bit SWrite transactions usign 16-bit deviceIDs suffer lost eofs - Version fixed : v4.4 - CR#467668 / AR#30322 - Modified Logical Layer to properly forward eof through the pipeline. - Some Logical Layer CARs are not being set correctly in the core. - Version fixed : v4.4 - CR#458414 / AR#30054 - The following Logical Layer CARs are not being set correctly in the core: - Assembly Information CAR (offset 0xC) - ExtendedFeaturesPtr portion - Processing Element Features CAR (offset 0x10) - Switch Port Information CAR (offset 0x14) - Destination Operations CAR (offset 0x1C) - Switch Route Table Destination ID Limit CAR (offset 0x34) - Core does not have functionality to enable the user to drop unintended packets based on Device ID. - Version fixed: v4.3. - CR#455552 - Added a new port called deviceid which indicates the current Device ID value stored in the Base Device ID CSR. - Receive side buffer design may corrupt packets - user may see corrupted packets from the logical layer when many small packets cause the status FIFO to fill. - Version fixed: v4.2 - CR#447884 / AR#29263 - No longer applicable, v5.1 introduces new buffer. - Repeated, transmitted packet accepted control symbols referencing the same AckID cause loss of AckID sync - The user will see this as potentially duplicated received packets which ultimately result in a port error condition. - Version fixed: v4.2 - CR#444561 / AR#29233 - Modified the transmit encoder to send a single packet accepted symbol per back-to-back control symbol. - Stomped packet sent after RFR (Restart-from-Retry)control symbol - The user will occasionally see error recovery on a retry which will affect system bandwidth. - Version fixed: v4.2 - CR#435188 / AR#24837 - Modified the PHY interface to kill a packet if discontinued on eof and prevent entry to the buffer. 5. KNOWN ISSUES The following are known issues for v5.5 of this core at time of release: - NGDBuild errors when using ISE GUI unless XST Keep Hierarchy set to Soft - Version to be fixed : Fix Not Scheduled - CR#534514 / AR#33528 - Please reference the Answer Record for additional information and recommendations. - Virtex-4 FX 3.125G, 4x core may not meet timing. - Version to be fixed : Fix Not Scheduled - CR#506364 / AR#32195 - Please reference the Answer Record for additional information and recommendations. - Unable to traindown to x1 mode in Lane 2. - Version to be fixed : Fix Not Scheduled - CR#457109 / AR#30023 - Traindown in Lane 0 works successfully but the Serial RapidIO endpoint is unable to traindown to Lane 2. The RocketIO transceivers only allow traindown to the channel bonding master. - Core reinitialization during error recovery causes recoverable protocol error. - Version to be fixed : Fix Not Scheduled - CR#457885 / AR#30021 - This is an corner condition that could occur if core is forced to reinitialize (i.e. - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable. - Post-Synplicity synthesis implementation runs may exhibit ucf failures - Version to be fixed : Fix Not Scheduled - CR#447782 / AR#29522 - Synplicity generated net names are not consistent with XST generated names and may not be consistent between core types. The .ucf file must be edited in these failure cases. Please reference the Serial RapidIO v5.1 web Release Notes for suggested work around. - PNA cause field may occasionally reflect a reserved value - Version to be fixed : Fix Not Scheduled - CR#436767 / AR#24982 - The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols. - Control Symbols may be lost on reinit - Version to be fixed : Fix Not Scheduled - CR#436768 / AR#24970 - This is an unusual and ultimately recoverable error. Set the "Additional Link Request Before Fatal" value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state. - Logical Rx does not support core side stalls - Version to be fixed : Fix Not Scheduled - CR#436770 / AR#24968 - The rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule. The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide located at www.xilinx.com/support/documentation/user_guides/xtp025.pdf 6. TECHNICAL SUPPORT To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 7. OTHER INFORMATION - N/A 8. CORE RELEASE HISTORY Date By Version Description ================================================================================ 04/2010 Xilinx, Inc. 5.5 5.0 Gbps support 03/2010 Xilinx, Inc. 5.4 Revision 1 11.5 support/Patch Release 09/2009 Xilinx, Inc. 5.4 Spartan-6 support 06/2009 Xilinx, Inc. 5.3 Virtex-6 support 04/2009 Xilinx, Inc. 5.2 11.1i support 11/2008 Xilinx, Inc. 5.1 Revision 1 Patch Release 09/2008 Xilinx, Inc. 5.1 New Buffer LogiCore 07/2008 Xilinx, Inc. 4.4 Revision 2 Patch Release 07/2008 Xilinx, Inc. 4.4 Revision 1 Patch Release 06/2008 Xilinx, Inc. 4.4 Bug Fixes 03/2008 Xilinx, Inc. 4.3 10.1i support 10/2007 Xilinx, Inc. 4.2 9.2i support 02/2007 Xilinx, Inc. 4.1 9.1i support 02/2006 Xilinx, Inc. 3.1 Revision 1 Patch Release 01/2006 Xilinx, Inc. 3.1 8.1i support ================================================================================ 9. Legal Disclaimer (c) Copyright 2006 - 2010 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
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