PCIe扫盲系列博文连载目录篇(第一阶段)

转载地址:http://blog.chinaaet.com/justlxy/p/5100053251

本文为PCIe扫盲系列博文连载目录篇(第一阶段),所谓第一阶段就是说后面还有第二阶段和第三阶段……第一阶段主要是介绍PCIe总线的发展历史与展望,PCI总线和PCI-X总线的简要回顾,PCIe总线的体系结构入门,PCIe总线的事务层、数据链路层,物理层入门;最后以一个简单的例子进行总结与回顾。

 

目录如下:

1、前言篇:PCIe扫盲——PCIe简介:http://blog.chinaaet.com/justlxy/p/5100053066

2、PCIe扫盲——PCI总线基本概念:http://blog.chinaaet.com/justlxy/p/5100053077

3、PCIe扫盲——一个典型的PCI总线周期:http://blog.chinaaet.com/justlxy/p/5100053078

4、PCIe扫盲——PCI总线中的Reflected-Wave Signaling:http://blog.chinaaet.com/justlxy/p/5100053079

5、PCIe扫盲——PCI总线的三种传输模式:http://blog.chinaaet.com/justlxy/p/5100053095

6、PCIe扫盲——PCI总线的中断和错误处理:http://blog.chinaaet.com/justlxy/p/5100053096

7、PCIe扫盲——PCI总线的地址空间分配:http://blog.chinaaet.com/justlxy/p/5100053219

8、PCIe扫盲——PCI总线配置周期产生和配置寄存器:http://blog.chinaaet.com/justlxy/p/5100053220

9、PCIe扫盲——66MHz的PCI总线与其技术瓶颈:http://blog.chinaaet.com/justlxy/p/5100053221

10、PCIe扫盲——PCI-X总线基本概念:http://blog.chinaaet.com/justlxy/p/5100053224

11、PCIe扫盲——PCIe总线基本概念:http://blog.chinaaet.com/justlxy/p/5100053225

12、PCIe扫盲——PCIe总线怎样做到在软件上兼容PCI总线:http://blog.chinaaet.com/justlxy/p/5100053245

13、PCIe扫盲——PCIe总线体系结构入门:http://blog.chinaaet.com/justlxy/p/5100053246

14、PCIe扫盲——PCIe总线事务层入门(一):http://blog.chinaaet.com/justlxy/p/5100053247

15、PCIe扫盲——PCIe总线事务层入门(二):http://blog.chinaaet.com/justlxy/p/5100053248

16、PCIe扫盲——PCIe总线事务层入门(三):http://blog.chinaaet.com/justlxy/p/5100053249

17、PCIe扫盲——PCIe总线数据链路层入门:http://blog.chinaaet.com/justlxy/p/5100053250

18、PCIe扫盲——PCIe总线物理层入门:http://blog.chinaaet.com/justlxy/p/5100053261

19、PCIe扫盲——一个Memory Read操作的例子:http://blog.chinaaet.com/justlxy/p/5100053263

 

第二阶段的目录篇地址为:http://blog.chinaaet.com/justlxy/p/5100053328

第三阶段的目录篇地址为:http://blog.chinaaet.com/justlxy/p/5100053481

第四阶段的目录篇地址为:http://blog.chinaaet.com/justlxy/p/5100057779

第五阶段的目录篇地址为:http://blog.chinaaet.com/justlxy/p/5100061871

Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.
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