VHDL练习_基本语法

--21片选
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity mux21 is
	port (
	a,b:	IN STD_LOGIC;
	s:		IN STD_LOGIC;
	y:		OUT STD_LOGIC
	);
END entity mux21;

architecture one of mux21 is 
begin
	y<=a when s='0' else
	   b when s='1';
end architecture;

--1位锁存器
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity latch is
	port (
		D:	IN STD_LOGIC;
		EN:	IN STD_LOGIC;
		Q:	OUT STD_LOGIC	
	);
end entity latch;
architecture one of latch is
signal sig_save : STD_LOGIC
begin
	process (D,EN)
	begin
		if EN = '1' then 
			sig_save <= D;
		end if;
		Q<=sig_save;
	end process;
end architecture one;

--全加器元件
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
	--或门
entity or2 is 
	port(
		a,b:	in STD_LOGIC;
		c:		out STD_LOGIC
	);
end entity or2;
architecture fun1 of or2 is 
begin
	c<= a or b;
end architecture fun1;
	-