//******************************************************************************
// MSP-FET430P140 Demo - Basic Clock, Implement Auto RSEL SW FLL
//
// Description: Set DCO clock to (Delta)*(4096) using software FLL. DCO clock
// is output on P5.5 as SMCLK. DCO clock, which is the selected SMCLK source
// for timer_A is integrated over LFXT1/8 (4096) until SMCLK is is equal
// to Delta. CCR2 captures ACLK. To use Set_DCO Timer_A must be
// operating in continous mode. Watch crystal for ACLK is required for
// this example. Delta must be kept in a range that allows possible
// DCO speeds. Minimum Delta must ensure that Set_DCO loop
// can complete within capture interval. Maximum delta can be calculated be
// f(DCOx7) / 4096. f(DCOx7) can be found in device specific datasheet.
// ACLK = LFXT1/8 = 32768/8, MCLK = SMCLK = target DCO
// //* External wat
// MSP-FET430P140 Demo - Basic Clock, Implement Auto RSEL SW FLL
//
// Description: Set DCO clock to (Delta)*(4096) using software FLL. DCO clock
// is output on P5.5 as SMCLK. DCO clock, which is the selected SMCLK source
// for timer_A is integrated over LFXT1/8 (4096) until SMCLK is is equal
// to Delta. CCR2 captures ACLK. To use Set_DCO Timer_A must be
// operating in continous mode. Watch crystal for ACLK is required for
// this example. Delta must be kept in a range that allows possible
// DCO speeds. Minimum Delta must ensure that Set_DCO loop
// can complete within capture interval. Maximum delta can be calculated be
// f(DCOx7) / 4096. f(DCOx7) can be found in device specific datasheet.
// ACLK = LFXT1/8 = 32768/8, MCLK = SMCLK = target DCO
// //* External wat