ChiselException: Cannot reassign to read-only

val shiftOut = RegInit(VecInit.fill(WINOGRAD_N, WINOGRAD_N)(0.U((ACC_W - 1).W)))  

for (i <- 0 until WINOGRAD_N) {
    for (j <- 0 until WINOGRAD_N) {
   
      // val bools = VecInit(shiftOut(i)(j).asBools)

      // for (k <- SHIFT_W until ACC_W - 1){
      //   bools(k) := (shiftOut(i)(j)(SHIFT_W - 1)).asBool
      // }

      // shiftOut(i)(j) := bools.asUInt
      shiftOut(i)(j)(ACC_W - 2, SHIFT_W) := Fill(ACC_W - 2 - SHIFT_W + 1, (shiftOut(i)(j)(SHIFT_W - 1)).asUInt)
      accIn(i)(j) := Mux((convertCntDelay(0)(3) === 0.U) & (convertCntDelay(1)(3) === 0.U), 0.S, accOut(i)(j))
      accValid(i)(j) := (((i.asUInt === 0.U) || (i.asUInt === (WINOGRAD_N - 1).U)) || (convertEnDelay(3)(1).asBool && (((j.asUInt === 0.U) || (j.asUInt === (WINOGRAD_N - 1).asUInt)) || convertEnDelay(3)(0).asBool)))

      val signedAddsubBypassAcc = Module(new SignedAddSubBypass(8, 1))
      signedAddsubBypassAcc.io.CLK := io.clk
      signedAddsubBypassAcc.io.CE := shiftOutValid
      signedAddsubBypassAcc.io.A := accIn(i)(j)
      signedAddsubBypassAcc.io.B := shiftOutMid(i)(j).asSInt
      // signedAddsubBypassAcc.io.B := shiftOut(i)(j)
      signedAddsubBypassAcc.io.B_ZERO := ~ accValid(i)(j)
      accOut(i)(j) := signedAddsubBypassAcc.io.C
    }
  }

Fix:

chisel 不支持part-select赋值

源码注释里就是fix