新版回来,由于demo板是8211的芯片,考虑成本更换成了8201芯片,
于是主要考虑的是硬件引脚的差异,因为软件demo的8201已经跑通;
然后主要是修改dts即可
diff --git a/kernel/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts b/kernel/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts
index 87a4994c0..858b79c0e 100755
--- a/kernel/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts
+++ b/kernel/arch/arm/boot/dts/rv1109-38-v10-spi-nand.dts
@@ -162,21 +162,28 @@
phy-mode = "rmii";
clock_in_out = "output";
- snps,reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
+ snps,reset-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 50000 50000>;
- assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
- assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>;
+ assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>;
+ assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>, <&cru RMII_MODE_CLK>;
assigned-clock-rates = <50000000>;
pinctrl-names = "default";
- pinctrl-0 = <&rmiim0_miim &rgmiim0_rxer &rmiim0_bus2 &rgmiim0_mclkinout_level0>;
+ pinctrl-0 = <&rmiim1_miim &rgmiim1_rxer &rmiim1_bus2 &rgmiim1_mclkinout_level0>;
phy-handle = <&phy>;
status = "okay";
};
&mdio {
- phy: phy@0 {
+ phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0x0>;
+ reg = <0x1>;
};
};
就是重m0口更换到m1口,然后一直不行,询问才知道是没有验证过的硬件;
于是硬件在原厂支持做了以下修改
总结就是:
1.给CRS_DV加了个下拉
2.把主控给出的芯片频率从XTAL_IN改成XTAL_OUT
===========================================================================
原理图
============================================================================
打上补丁:20201120_SZ18201_phy_support.patch
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
old mode 100644
new mode 100755
index 58a490e..0097355
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -85,9 +85,11 @@ MODULE_PARM_DESC(pause, "Flow Control Pause Time");
static int tc = TC_DEFAULT;
module_param(tc, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(tc, "DMA threshold control value");
static int buf_sz = DEFAULT_BUFSIZE;
+
+#define SZ18201_PHY_ID 0x00000128
+
module_param(buf_sz, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(buf_sz, "DMA buffer size");
@@ -2858,6 +2860,28 @@ static void stmmac_scan_delayline_dwork(struct work_struct *work)
};
#endif
+
+static int SZ18201_PHY_fixup(struct phy_device *phydev)
+{
+ u16 value;
+ printk("%s in\n